riscv/rocket-chip
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only write out finish from tile 0 in groundtest

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This commit is contained in:
Howard Mao 2016-05-03 13:09:22 -07:00
parent b95f095aca
commit 518d510622
1 changed files with 10 additions and 7 deletions
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17
groundtest/src/main/scala/tile.scala
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@ -137,7 +137,7 @@ class GroundTestFinisher(implicit p: Parameters) extends TLModule()(p) {
}
class GroundTestTile(id: Int, resetSignal: Bool)
(implicit val p: Parameters) extends Tile(resetSignal)(p) {
(implicit val p: Parameters) extends Tile(resetSignal)(p) {
val test = p(BuildGroundTest)(id, dcacheParams)
@ -151,11 +151,14 @@ class GroundTestTile(id: Int, resetSignal: Bool)
ptw.io.requestors(0) <> test.io.ptw
ptw.io.requestors(1) <> dcache.io.ptw
val finisher = Module(new GroundTestFinisher)
finisher.io.finished := test.io.finished
// Only Tile 0 needs to write tohost
if (id == 0) {
val finisher = Module(new GroundTestFinisher)
finisher.io.finished := test.io.finished
val memArb = Module(new ClientUncachedTileLinkIOArbiter(2))
memArb.io.in(0) <> test.io.mem
memArb.io.in(1) <> finisher.io.mem
io.uncached.head <> memArb.io.out
val memArb = Module(new ClientUncachedTileLinkIOArbiter(2))
memArb.io.in(0) <> test.io.mem
memArb.io.in(1) <> finisher.io.mem
io.uncached.head <> memArb.io.out
} else { io.uncached.head <> test.io.mem }
}