riscv/rocket-chip
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Author SHA1 Message Date
Andrew WatermanandGitHub 9751ea0f35 Fix Verilator VCD (#157) 2016-07-09 02:37:39 -07:00
Andrew WatermanandGitHub 70b677ecda Vec considered harmful; use isOneOf instead (#64) 
Vec is heavyweight and really should only be used for I/O and
dynamic indexing.  A recurring pattern in uncore is

    Vec(const1, const2, const3) contains x

which is nice but has a deleterious effect on simulation copilation
and execution time.  This patch proposes an alternative:

    x isOneOf (const1, const2, const3)
    x isOneOf seqOfThings

I think it's also more idiomatic.

This is just a prototype; I'm not wed to the name or implementation.
 2016-07-07 19:25:57 -07:00
Andrew Waterman d24c87f8ba Update PLIC/PRCI address map (#124) 2016-06-06 04:51:55 -07:00
Andrew Waterman ece3ab9c3d Refactor AddrMap and its usage (#122) 2016-06-03 17:29:05 -07:00
Andrew Waterman c8338ad809 Instantiate Debug Module (#119) 2016-06-02 10:53:41 -07:00
Andrew Waterman c49cb10c74 Merge pull request #42 from terpstra/ahb 
Ahb
 2016-05-24 17:02:15 -07:00
Andrew Waterman d1639416cb Merge pull request #77 from ucb-bar/chisel3 
Preliminary Chisel 3 Support
 2016-03-24 12:56:36 -07:00
Andrew Waterman 648437e7cb Merge pull request #70 from ucb-bar/add-rv32-support 
Add RV32 test/configuration options
 2016-03-14 17:06:39 -07:00
Andrew Waterman f2ded2721d Merge branch 'master' into add-rv32-support 2016-03-10 19:33:04 -08:00
Andrew Waterman 67ad36d74a Merge pull request #69 from ucb-bar/fix-tabs 
tabs are evil
 2016-03-10 16:17:46 -08:00
Andrew Waterman 640204b221 Merge pull request #66 from ucb-bar/rocc-ptw-refactoring 
RoCC PTW refactoring
 2016-02-25 18:01:01 -08:00
Andrew Waterman 70945953a8 Merge pull request #42 from ucb-bar/chisel3 
Chisel 3 support
 2016-02-05 16:01:35 -08:00
Andrew Waterman 7e9d8c7256 Merge pull request #40 from ucb-bar/make-3.82 
Support make-3.82 and newer
 2016-01-28 14:28:27 -08:00
Andrew Waterman 91be080526 Merge pull request #32 from ucb-bar/javamaxpermsize 
Double Java MaxPermSize.
 2015-12-07 13:58:41 -08:00
Andrew Waterman d08b75c472 Merge pull request #15 from ucb-bar/fix_disasm_garbage 
If you don't have spike-disasm in your path, your path is dumped
 2015-09-03 17:55:31 -07:00
Andrew Waterman 25e1412a33 Merge pull request #11 from ucb-bar/regression-fixes 
Regression script fixes
 2015-07-20 12:58:54 -07:00
Andrew Waterman 1ae7a9376c Fix unhandled LLC writeback hazard 2014-06-13 03:25:52 -07:00
Andrew Waterman 364a6de214 Use Mem instead of Vec[Reg] 2014-05-18 19:26:35 -07:00
Andrew Waterman fb8c7d3da5 Push rocket 2014-04-07 23:49:06 -07:00
Andrew Waterman 817517c663 Better branch prediction 2014-04-07 16:08:06 -07:00
Andrew Waterman 51808d9982 Fix minor FP bugs 2014-03-18 18:37:53 -07:00
Andrew Waterman 0d124d283a Write our own vcs main() routine 2014-03-17 17:02:28 -07:00
Andrew Waterman 7f23257873 Print out random seed if test fails 2014-03-17 15:35:32 -07:00
Andrew Waterman fcbbb275aa Fix nondeterminism 2014-03-15 17:35:30 -07:00
Andrew Waterman b6bf7cfe0c push chisel 2014-03-11 23:56:57 -07:00
Andrew Waterman 7ac003a4f7 push hardfloat 2014-03-11 20:36:39 -07:00
Andrew Waterman f04bde75fb New FP encoding 2014-03-11 19:12:20 -07:00
Andrew Waterman d055c0ebaf Push rocket/hardfloat/chisel 2014-03-04 16:39:06 -08:00
Andrew Waterman de965d558a Renumber uarch CSRs into custom CSR space 2014-02-14 17:41:17 -08:00
Andrew Waterman e554f6728d Update chisel 2014-02-14 17:41:17 -08:00
Andrew Waterman 02dbd6b0aa Don't assign to your own inputs 2014-02-12 18:39:40 -08:00
Andrew Waterman e5de170215 Update Chisel, fixing Verilog backend 2014-02-12 14:28:43 -08:00
Andrew Waterman 0ebb115a3c Revert to old AUIPC definition 2014-02-10 19:05:14 -08:00
Andrew Waterman 11e69a73cd Fix tests when !hwacha; disable hwacha by default 2014-02-06 03:08:33 -08:00
Andrew Waterman e9d3a650a4 Speed up C++ compilation 2014-01-31 12:25:19 -08:00
Andrew Waterman 0ce98a7e0c Update riscv-tools 2014-01-28 03:52:55 -08:00
Andrew Waterman fb827abbfa Use dynamic fesvr library 2014-01-28 03:50:19 -08:00
Andrew Waterman 3e634aef1d Fix HTIF for cache line sizes other than 64 B 2014-01-22 18:20:36 -08:00
Andrew Waterman 7c11cf49b8 Update riscv-tools 2014-01-21 16:23:32 -08:00
Andrew Waterman b6c6bddb62 Add full CSRRx support and an asm test 2014-01-21 16:20:24 -08:00
Andrew Waterman 6f7ae01b1a More FPU fixes 2014-01-17 14:10:10 -08:00
Andrew Waterman 6f028b2d52 Increase BTB size; fix Rocket FPU bug 2014-01-17 03:53:08 -08:00
Andrew Waterman dfc13236d1 Linux works again! 2014-01-16 12:44:29 -08:00
Andrew Waterman 4f1213cb8b Fix Scala integer overflow 2014-01-13 21:45:14 -08:00
Andrew Waterman d99ee1f9c2 Update hardfloat, fixing SFMA unit 2013-12-09 20:31:58 -08:00
Andrew Waterman ab6cd9c9e8 Update chisel, rocket 2013-12-09 15:09:48 -08:00
Andrew Waterman a43cf9d688 Update to new privileged ISA 2013-11-25 04:45:06 -08:00
Andrew Waterman acc0d2b06c Only use LSBs for HTIF control regs 
For now, at least...
 2013-11-25 04:34:16 -08:00
Andrew Waterman a875233be6 update subrepos 2013-10-29 21:17:07 -07:00
Andrew Waterman 3c1d1f7981 Fix(?) SBT race by defining subproject build order 2013-10-29 13:27:36 -07:00
Andrew Waterman 8c380a7c3a Abort "make run" when tests fail 2013-10-29 13:25:57 -07:00
Andrew Waterman c55eee7244 Pass target machine exit code back to host OS 2013-10-29 13:24:09 -07:00
Andrew WatermanandHenry Cook 8e926f8d79 remove aborts 2013-03-25 17:01:46 -07:00
Andrew WatermanandHenry Cook ce4c1aa566 remove aborts 2013-03-25 17:01:46 -07:00
Andrew Waterman 7b019cb0da rmeove aborts 2013-03-19 15:30:23 -07:00
Andrew Waterman bbd010750f add missing #include 2013-01-06 04:53:40 -08:00
Andrew Waterman fd727bf8aa add some of the zedboard fpga infrastructure 
you can elaborate the RTL in fpga/build/vcs-sim-rtl, but there's no harness
for VCS simulation yet.
 2013-01-06 03:58:10 -08:00
Andrew Waterman 03df2c3766 update .gitignores 2013-01-06 03:58:10 -08:00
Andrew Waterman 10a6a42a4a make vlsi use dram model by default 2012-12-06 03:13:45 -08:00
Andrew Waterman aae7a67781 fix llc refill/writeback bugs 2012-12-06 02:07:03 -08:00
Andrew Waterman d911e635d6 simplify c++ memory models; support +dramsim flag 
works for both vlsi and emulator
 2012-12-04 07:04:26 -08:00
Andrew Waterman 50e9d952e8 don't initiate llc refill until writeback drains 2012-12-04 06:57:53 -08:00
Andrew Waterman 5dfb388f03 update to newest rocket 2012-11-27 02:43:31 -08:00
Andrew Waterman ea7029484e update to latest rocket 2012-11-26 20:57:12 -08:00
Andrew Waterman 8103676b37 reduce physical address space to 4GB 2012-11-26 20:54:56 -08:00
Andrew Waterman e12af07722 update to newest rocket 2012-11-25 04:40:46 -08:00
Andrew Waterman 9372912a9c update to newest rocket 2012-11-20 05:42:44 -08:00
Andrew Waterman 6d47d18c2b catch sigterm to gracefully exit (fixes vcd) 2012-11-20 05:40:44 -08:00
Andrew Waterman 7330deb13a print stack trace if elaboration fails 2012-11-20 05:39:48 -08:00
Andrew Waterman 56f9b9721d treat prefetches as read requests 2012-11-20 05:38:49 -08:00
Andrew Waterman 7bcf59a18f support continous compilation via "make test" 
for c++ emulator only, for now
 2012-11-17 19:58:18 -08:00
Andrew Waterman b58214d7e3 remove more global constants 2012-11-17 17:25:43 -08:00
Andrew Waterman cf05b604b3 upgrade to new rocket; improve vlsi makefiles 2012-11-17 07:21:29 -08:00
Andrew Waterman 672e904c86 update to new rocket/uncore 2012-11-16 02:41:50 -08:00
Andrew Waterman 3e6dc35809 issue self-probes for uncached read transactions 
this facilitates I$ coherence.  but it seems like a hack and perhaps
the mechanism should be rethought.
 2012-11-16 02:37:56 -08:00
Andrew Waterman e2afae011a factor out global constants 2012-11-06 08:18:40 -08:00
Andrew Waterman 0c372fc9ec refactor I$ config into RocketConfiguration 2012-11-04 17:00:19 -08:00
Andrew Waterman 4ed2d614a2 update to new rocket; retime fpu in dc-syn 2012-11-04 16:43:02 -08:00
Andrew Waterman 367b5489d1 first crack at continuous compilation/testing flow 
try it out: cd emulator; make test
 2012-10-19 04:09:07 -07:00
Andrew Waterman 1ad928cfe2 directly integrate dramsim build 
also, build it as a static library to simplify dependencies
 2012-10-18 18:59:37 -07:00
Andrew Waterman edf0eeed01 integrate updated rocket/uncore 2012-10-18 17:51:41 -07:00
Andrew Waterman 2aecb0024f UncoreConfiguration now contains coherence policy 2012-10-18 16:57:28 -07:00
Andrew Waterman ffda0e41a9 parameterize width of MemSerdes/MemDesser 2012-10-18 16:56:36 -07:00
Andrew Waterman 7fd4eb6afd update uncore 2012-10-09 18:05:32 -07:00
Andrew Waterman 3973aef938 handle structural hazard on LLC tags 2012-10-09 18:04:55 -07:00
Andrew Waterman c3236e6ee6 add missing symlink and update uncore 2012-10-09 17:51:33 -07:00
Andrew Waterman 17dc2075dd fix some LLC control bugs 2012-08-06 17:10:04 -07:00
Andrew Waterman 115c25c34b fix some LLC control bugs 2012-08-06 17:10:04 -07:00
Andrew Waterman 875f3622af fix deadlock in coherence hub 2012-08-03 19:00:03 -07:00
Andrew Waterman 962423d2d1 fix deadlock in coherence hub 2012-08-03 19:00:03 -07:00
Andrew Waterman e346f21725 fix control bug in LLC 
structural hazard on tag ram caused deadlock
 2012-08-03 18:59:37 -07:00
Andrew Waterman 92b7504c9a fix control bug in LLC 
structural hazard on tag ram caused deadlock
 2012-08-03 18:59:37 -07:00
Andrew Waterman 7a75334bb9 pipeline LLC further 2012-07-31 17:45:14 -07:00
Andrew Waterman 7b9cfd0b90 pipeline LLC further 2012-07-31 17:45:14 -07:00
Andrew Waterman 8db233c9b7 further pipeline the LLC 2012-07-30 20:12:11 -07:00
Andrew Waterman 85dc34df80 further pipeline the LLC 2012-07-30 20:12:11 -07:00
Andrew Waterman 1ae3091261 memory system bug fixes 2012-07-26 00:05:21 -07:00
Andrew Waterman 1405718ca8 memory system bug fixes 2012-07-26 00:05:21 -07:00
Andrew Waterman df8aff0906 don't dequeue probe queue during reset 2012-07-22 21:05:52 -07:00
Andrew Waterman c6ac836581 don't dequeue probe queue during reset 2012-07-22 21:05:52 -07:00