riscv/rocket-chip
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remove more global constants

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This commit is contained in:
Andrew Waterman 2012-11-17 17:25:43 -08:00
parent cf05b604b3
commit b58214d7e3
3 changed files with 5 additions and 4 deletions
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4
csrc/emulator.cc
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@ -54,7 +54,7 @@ int main(int argc, char** argv)
demand(fcntl(fromhost_fd,F_GETFD) >= 0, "fromhost file not open");
demand(fcntl(tohost_fd,F_GETFD) >= 0, "tohost file not open");
const size_t disasm_len = 24;
const int disasm_len = 24;
if (vcd)
{
// Create a VCD file
@ -157,7 +157,7 @@ int main(int argc, char** argv)
{
wb_disasm.resize(disasm_len, ' ');
dat_t<disasm_len*8> disasm_dat;
for (size_t i = 0; i < disasm_len; i++)
for (int i = 0; i < disasm_len; i++)
disasm_dat = disasm_dat << 8 | LIT<8>(wb_disasm[i]);
tile.dump(vcdfile, trace_count);

2
riscv-rocket

@ -1 +1 @@
Subproject commit 7a225aac9ec81d59d6e161cd9ea554b00b0d0906
Subproject commit 238b637fb2bad9da4c935993dc937523fdf5938b

3
src/main/scala/RocketChip.scala
View File

@ -210,7 +210,8 @@ class Top extends Component {
val ic = ICacheConfig(128, 2, co)
val dc = DCacheConfig(128, 4, co,
nmshr = 2, nrpq = 16, nsdq = 17)
val rc = RocketConfiguration(NTILES, co, ic, dc)
val rc = RocketConfiguration(NTILES, co, ic, dc,
fpu = true, vec = false)
val tile = new Tile(resetSignal = hl.reset)(rc)
tile.io.host.reset := Reg(Reg(hl.reset))