riscv/rocket-chip
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Rocket Chip Generator (https://github.com/freechipsproject/rocket-chip)
217 Commits 1 Branch 0 Tags 13 MiB
Scala 93.1%
C++ 2.1%
Python 2%
Makefile 1.2%
Verilog 0.8%
Other 0.7%
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Andrew Waterman acc0d2b06c Only use LSBs for HTIF control regs 
For now, at least...
2013-11-25 04:34:16 -08:00
uncore Only use LSBs for HTIF control regs 2013-11-25 04:34:16 -08:00