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riscv
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rocket-chip
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acc0d2b06c6007993552cf949fcd3af809b5ce54
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Andrew Waterman
acc0d2b06c
Only use LSBs for HTIF control regs
...
For now, at least...
2013-11-25 04:34:16 -08:00
uncore
Only use LSBs for HTIF control regs
2013-11-25 04:34:16 -08:00
Description
Rocket Chip Generator (
https://github.com/freechipsproject/rocket-chip
)
13
MiB
Languages
Scala
93.1%
C++
2.1%
Python
2%
Makefile
1.2%
Verilog
0.8%
Other
0.7%