riscv/rocket-chip
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update to newest rocket

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This commit is contained in:
Andrew Waterman
2012-11-25 04:40:46 -08:00
parent 9372912a9c
commit e12af07722
4 changed files with 6 additions and 6 deletions
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2
chisel

Submodule chisel updated: 1f29014029...32aad63fa3

4
emulator/Makefile
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@ -12,8 +12,8 @@ CXXFLAGS := $(CXXFLAGS) -Itestbench -I$(basedir)/chisel/csrc -I../dramsim2
OBJS := $(addsuffix .o,$(CXXSRCS) $(MODEL))
DEBUG_OBJS := $(addsuffix -debug.o,$(CXXSRCS) $(MODEL))
CHISEL_ARGS := $(MODEL) --backend c --targetDir ../emulator/generated-src
CHISEL_ARGS_DEBUG := $(CHISEL_ARGS)-debug --debug --vcd
CHISEL_ARGS := $(MODEL) --noIoDebug --backend c --targetDir ../emulator/generated-src
CHISEL_ARGS_DEBUG := $(CHISEL_ARGS)-debug --debug --vcd --ioDebug
generated-src/$(MODEL).cpp: $(basedir)/riscv-rocket/src/*.scala $(basedir)/riscv-hwacha/src/*.scala $(basedir)/chisel/src/main/scala/* $(basedir)/uncore/src/*.scala
cd $(basedir)/sbt && $(SBT) "project referencechip" "elaborate $(CHISEL_ARGS)"

2
riscv-rocket

Submodule riscv-rocket updated: d568979ccb...c89f0033f4

4
src/main/scala/RocketChip.scala
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@ -207,8 +207,8 @@ class Top extends Component {
val hl = uncore.io.htif(i)
val tl = uncore.io.tiles(i)
val ic = ICacheConfig(128, 2, co)
val dc = DCacheConfig(128, 4, co,
val ic = ICacheConfig(128, 2, co, ntlb = 8, nbtb = 16)
val dc = DCacheConfig(128, 4, co, ntlb = 8,
nmshr = 2, nrpq = 16, nsdq = 17)
val rc = RocketConfiguration(NTILES, co, ic, dc,
fpu = true, vec = true)