simplify c++ memory models; support +dramsim flag
works for both vlsi and emulator
This commit is contained in:
parent
5dfb388f03
commit
d911e635d6
8
Makefrag
8
Makefrag
@ -2,10 +2,16 @@
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MODEL := Top
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CXX := g++
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CXXFLAGS := -O2
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CXXFLAGS := -O2 -g
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SBT := java -Xmx2048M -Xss8M -XX:MaxPermSize=128M -jar sbt-launch.jar
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DRAMSIM_OBJS := $(patsubst %.cpp,%.o,$(wildcard $(basedir)/dramsim2/*.cpp))
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$(DRAMSIM_OBJS): %.o: %.cpp
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$(CXX) $(CXXFLAGS) -DNO_STORAGE -DNO_OUTPUT -Dmain=nomain -c -o $@ $<
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libdramsim.a: $(DRAMSIM_OBJS)
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ar rcs $@ $^
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#--------------------------------------------------------------------
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# Tests
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#--------------------------------------------------------------------
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2
chisel
2
chisel
@ -1 +1 @@
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Subproject commit 14a2dfa4be88f60965476207872a26bd1b68448c
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Subproject commit 2387c2d41ba2239c8939c1a0819201db300297d5
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@ -6,8 +6,8 @@
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#include <map>
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#include "common.h"
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#include "emulator.h"
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//#include "mm_emulator.cc"
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#include "mm_emulator_dramsim2.cc"
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#include "mm.h"
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#include "mm_dramsim2.h"
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#include "Top.h" // chisel-generated code...
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#include "disasm.h"
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@ -31,6 +31,7 @@ int main(int argc, char** argv)
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FILE *vcdfile = NULL, *logfile = stderr;
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const char* failure = NULL;
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disassembler disasm;
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bool dramsim2 = false;
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signal(SIGTERM, handle_sigterm);
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@ -41,6 +42,8 @@ int main(int argc, char** argv)
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log = true;
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else if (arg == "-q")
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quiet = true;
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else if (arg == "+dramsim")
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dramsim2 = true;
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else if (arg.substr(0, 2) == "-v")
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vcd = argv[i]+2;
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else if (arg.substr(0, 2) == "-m")
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@ -75,11 +78,10 @@ int main(int argc, char** argv)
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fprintf(vcdfile, "$upscope $end\n");
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}
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// basic fixed latency memory model
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/*uint64_t* mem = mm_init();*/
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uint64_t* mm_mem = dramsim2_init();
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if (loadmem != NULL)
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load_mem(mm_mem, loadmem);
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mm_t* mm = dramsim2 ? (mm_t*)(new mm_dramsim2_t) : (mm_t*)(new mm_magic_t);
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mm->init(MEM_SIZE);
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if (loadmem)
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load_mem(mm->get_data(), loadmem);
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// The chisel generated code
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@ -101,25 +103,11 @@ int main(int argc, char** argv)
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while (!exit_now)
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{
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// fprintf(stderr, "trace count: %ld\n", trace_count);
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// memory model
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// mm_tick_emulator(
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dramsim2_tick_emulator (
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tile.Top__io_mem_req_cmd_valid.lo_word(),
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&tile.Top__io_mem_req_cmd_ready.values[0],
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tile.Top__io_mem_req_cmd_bits_rw.lo_word(),
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tile.Top__io_mem_req_cmd_bits_addr.lo_word(),
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tile.Top__io_mem_req_cmd_bits_tag.lo_word(),
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tile.Top__io_mem_req_data_valid.lo_word(),
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&tile.Top__io_mem_req_data_ready.values[0],
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&tile.Top__io_mem_req_data_bits_data.values[0],
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&tile.Top__io_mem_resp_valid.values[0],
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&tile.Top__io_mem_resp_bits_tag.values[0],
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&tile.Top__io_mem_resp_bits_data.values[0]
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);
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// fprintf(stderr, "trace count: %ld (after dramsim2_tick_emulator)\n", trace_count);
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tile.Top__io_mem_req_cmd_ready = LIT<1>(mm->req_cmd_ready());
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tile.Top__io_mem_req_data_ready = LIT<1>(mm->req_data_ready());
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tile.Top__io_mem_resp_valid = LIT<1>(mm->resp_valid());
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tile.Top__io_mem_resp_bits_tag = LIT<64>(mm->resp_tag());
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memcpy(&tile.Top__io_mem_resp_bits_data, mm->resp_data(), tile.Top__io_mem_resp_bits_data.width()/8);
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tile.Top__io_host_in_valid = LIT<1>(htif_phy.in_valid());
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tile.Top__io_host_in_bits = LIT<64>(htif_phy.in_bits());
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@ -127,6 +115,16 @@ int main(int argc, char** argv)
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tile.clock_lo(LIT<1>(0));
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mm->tick(
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tile.Top__io_mem_req_cmd_valid.lo_word(),
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tile.Top__io_mem_req_cmd_bits_rw.lo_word(),
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tile.Top__io_mem_req_cmd_bits_addr.lo_word(),
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tile.Top__io_mem_req_cmd_bits_tag.lo_word(),
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tile.Top__io_mem_req_data_valid.lo_word(),
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&tile.Top__io_mem_req_data_bits_data.values[0]
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);
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if (tile.Top__io_host_clk_edge.to_bool())
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{
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htif_phy.tick(tile.Top__io_host_in_ready.lo_word(),
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90
csrc/mm.cc
Normal file
90
csrc/mm.cc
Normal file
@ -0,0 +1,90 @@
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#include "mm.h"
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#include <iostream>
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#include <fstream>
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#include <cstdlib>
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#include <cstring>
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#include <cassert>
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void mm_t::init(size_t sz)
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{
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data = new char[sz];
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size = sz;
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}
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mm_t::~mm_t()
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{
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delete [] data;
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}
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void mm_magic_t::init(size_t sz)
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{
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mm_t::init(sz);
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dummy_data.resize(MM_WORD_SIZE);
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}
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void mm_magic_t::tick
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(
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bool req_cmd_val,
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bool req_cmd_store,
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uint64_t req_cmd_addr,
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uint64_t req_cmd_tag,
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bool req_data_val,
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void* req_data_bits
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)
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{
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bool req_cmd_fire = req_cmd_val && req_cmd_ready();
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bool req_data_fire = req_data_val && req_data_ready();
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assert(!(req_cmd_fire && req_data_fire));
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if (resp_valid())
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resp.pop();
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if (req_data_fire)
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{
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memcpy(data + store_addr + store_count*MM_WORD_SIZE, req_data_bits, MM_WORD_SIZE);
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store_count = (store_count + 1) % REFILL_COUNT;
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if (store_count == 0)
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store_inflight = false;
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}
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if (req_cmd_fire)
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{
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auto byte_addr = req_cmd_addr*REFILL_COUNT*MM_WORD_SIZE;
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assert(byte_addr < size);
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if (req_cmd_store)
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{
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store_inflight = true;
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store_addr = byte_addr;
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}
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else for (int i = 0; i < REFILL_COUNT; i++)
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{
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auto base = data + byte_addr + i*MM_WORD_SIZE;
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auto dat = std::vector<char>(base, base + MM_WORD_SIZE);
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resp.push(std::make_pair(req_cmd_tag, dat));
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}
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}
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cycle++;
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}
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void load_mem(void* mem, const char* fn)
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{
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char* m = (char*)mem;
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std::ifstream in(fn);
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if (!in)
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{
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std::cerr << "could not open " << fn << std::endl;
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exit(-1);
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}
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std::string line;
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while (std::getline(in, line))
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{
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#define parse_nibble(c) ((c) >= 'a' ? (c)-'a'+10 : (c)-'0')
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for (ssize_t i = line.length()-2, j = 0; i >= 0; i -= 2, j++)
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m[j] = (parse_nibble(line[i]) << 4) | parse_nibble(line[i+1]);
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m += line.length()/2;
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}
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}
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75
csrc/mm.h
Normal file
75
csrc/mm.h
Normal file
@ -0,0 +1,75 @@
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#ifndef MM_EMULATOR_H
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#define MM_EMULATOR_H
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#include "mm_param.h"
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#include <stdint.h>
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#include <queue>
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class mm_t
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{
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public:
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mm_t() : data(0), size(0) {}
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virtual void init(size_t sz);
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virtual bool req_cmd_ready() = 0;
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virtual bool req_data_ready() = 0;
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virtual bool resp_valid() = 0;
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virtual uint64_t resp_tag() = 0;
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virtual void* resp_data() = 0;
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virtual void tick
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(
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bool req_cmd_val,
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bool req_cmd_store,
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uint64_t req_cmd_addr,
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uint64_t req_cmd_tag,
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bool req_data_val,
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void* req_data_bits
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) = 0;
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virtual void* get_data() { return data; }
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virtual size_t get_size() { return size; }
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virtual ~mm_t();
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protected:
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char* data;
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size_t size;
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};
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class mm_magic_t : public mm_t
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{
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public:
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mm_magic_t() : store_inflight(false), store_count(0) {}
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virtual void init(size_t sz);
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virtual bool req_cmd_ready() { return !store_inflight; }
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virtual bool req_data_ready() { return store_inflight; }
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virtual bool resp_valid() { return !resp.empty(); }
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virtual uint64_t resp_tag() { return resp_valid() ? resp.front().first : 0; }
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virtual void* resp_data() { return resp_valid() ? &resp.front().second[0] : &dummy_data[0]; }
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virtual void tick
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(
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bool req_cmd_val,
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bool req_cmd_store,
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uint64_t req_cmd_addr,
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uint64_t req_cmd_tag,
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bool req_data_val,
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void* req_data_bits
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);
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protected:
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bool store_inflight;
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int store_count;
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uint64_t store_addr;
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std::vector<char> dummy_data;
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uint64_t cycle;
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std::queue<std::pair<uint64_t, std::vector<char>>> resp;
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};
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void load_mem(void* mem, const char* fn);
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#endif
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122
csrc/mm_dramsim2.cc
Normal file
122
csrc/mm_dramsim2.cc
Normal file
@ -0,0 +1,122 @@
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#include "mm_dramsim2.h"
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#include "mm.h"
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#include <DRAMSim.h>
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#include <iostream>
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#include <fstream>
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#include <list>
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#include <queue>
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#include <cstring>
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#include <cstdlib>
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#include <cassert>
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//#define DEBUG_DRAMSIM2
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using namespace DRAMSim;
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void mm_dramsim2_t::read_complete(unsigned id, uint64_t address, uint64_t clock_cycle)
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{
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assert(req.count(address));
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auto tag = req[address];
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req.erase(address);
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for (int i = 0; i < REFILL_COUNT; i++)
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{
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auto base = data + address + i*MM_WORD_SIZE;
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auto dat = std::vector<char>(base, base + MM_WORD_SIZE);
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resp.push(std::make_pair(tag, dat));
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}
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#ifdef DEBUG_DRAMSIM2
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fprintf(stderr, "[Callback] read complete: id=%d , addr=0x%lx , cycle=%lu\n", id, address, clock_cycle);
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#endif
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}
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void mm_dramsim2_t::write_complete(unsigned id, uint64_t address, uint64_t clock_cycle)
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{
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#ifdef DEBUG_DRAMSIM2
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fprintf(stderr, "[Callback] write complete: id=%d , addr=0x%lx , cycle=%lu\n", id, address, clock_cycle);
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#endif
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}
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void power_callback(double a, double b, double c, double d)
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{
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//fprintf(stderr, "power callback: %0.3f, %0.3f, %0.3f, %0.3f\n",a,b,c,d);
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}
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void mm_dramsim2_t::init(size_t sz)
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{
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mm_t::init(sz);
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dummy_data.resize(MM_WORD_SIZE);
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assert(size % (1024*1024) == 0);
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mem = getMemorySystemInstance("DDR3_micron_64M_8B_x4_sg15.ini", "system.ini", "dramsim2_ini", "results", size/(1024*1024));
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TransactionCompleteCB *read_cb = new Callback<mm_dramsim2_t, void, unsigned, uint64_t, uint64_t>(this, &mm_dramsim2_t::read_complete);
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TransactionCompleteCB *write_cb = new Callback<mm_dramsim2_t, void, unsigned, uint64_t, uint64_t>(this, &mm_dramsim2_t::write_complete);
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mem->RegisterCallbacks(read_cb, write_cb, power_callback);
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#ifdef DEBUG_DRAMSIM2
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fprintf(stderr,"Dramsim2 init successful\n");
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#endif
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}
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void mm_dramsim2_t::tick
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(
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bool req_cmd_val,
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bool req_cmd_store,
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uint64_t req_cmd_addr,
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uint64_t req_cmd_tag,
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bool req_data_val,
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void* req_data_bits
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)
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{
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bool req_cmd_fire = req_cmd_val && req_cmd_ready();
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bool req_data_fire = req_data_val && req_data_ready();
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assert(!(req_cmd_fire && req_data_fire));
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if (resp_valid())
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resp.pop();
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if (req_cmd_fire)
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{
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auto byte_addr = req_cmd_addr*REFILL_COUNT*MM_WORD_SIZE;
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assert(byte_addr < size);
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if (req_cmd_store)
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{
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store_inflight = 1;
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store_addr = byte_addr;
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#ifdef DEBUG_DRAMSIM2
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fprintf(stderr, "Starting store transaction (addr=%lx ; tag=%ld ; cyc=%ld)\n", store_addr, req_cmd_tag, cycle);
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#endif
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}
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else
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{
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assert(!req.count(byte_addr));
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req[byte_addr] = req_cmd_tag;
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mem->addTransaction(false, byte_addr);
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#ifdef DEBUG_DRAMSIM2
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fprintf(stderr, "Adding load transaction (addr=%lx; cyc=%ld)\n", byte_addr, cycle);
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#endif
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}
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}
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if (req_data_fire)
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{
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memcpy(data + store_addr + store_count*MM_WORD_SIZE, req_data_bits, MM_WORD_SIZE);
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store_count = (store_count + 1) % REFILL_COUNT;
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if (store_count == 0)
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{ // last chunch of cache line arrived.
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store_inflight = 0;
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mem->addTransaction(true, store_addr);
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#ifdef DEBUG_DRAMSIM2
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fprintf(stderr, "Adding store transaction (addr=%lx; cyc=%ld)\n", store_addr, cycle);
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#endif
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}
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}
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mem->update();
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cycle++;
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}
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50
csrc/mm_dramsim2.h
Normal file
50
csrc/mm_dramsim2.h
Normal file
@ -0,0 +1,50 @@
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#ifndef _MM_EMULATOR_DRAMSIM2_H
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#define _MM_EMULATOR_DRAMSIM2_H
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#include "mm.h"
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#include <DRAMSim.h>
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#include <map>
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#include <queue>
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#include <stdint.h>
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class mm_dramsim2_t : public mm_t
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{
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public:
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mm_dramsim2_t() : store_inflight(false), store_count(0) {}
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virtual void init(size_t sz);
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virtual bool req_cmd_ready() { return mem->willAcceptTransaction() && !store_inflight; }
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virtual bool req_data_ready() { return mem->willAcceptTransaction() && store_inflight; }
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virtual bool resp_valid() { return !resp.empty(); }
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virtual uint64_t resp_tag() { return resp_valid() ? resp.front().first : 0; }
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virtual void* resp_data() { return resp_valid() ? &resp.front().second[0] : &dummy_data[0]; }
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virtual void tick
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(
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bool req_cmd_val,
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bool req_cmd_store,
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uint64_t req_cmd_addr,
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uint64_t req_cmd_tag,
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bool req_data_val,
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void* req_data_bits
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);
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protected:
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DRAMSim::MultiChannelMemorySystem *mem;
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uint64_t cycle;
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bool store_inflight;
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int store_count;
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uint64_t store_addr;
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std::vector<char> dummy_data;
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std::map<uint64_t,uint64_t> req;
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std::queue<std::pair<uint64_t, std::vector<char>>> resp;
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void read_complete(unsigned id, uint64_t address, uint64_t clock_cycle);
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void write_complete(unsigned id, uint64_t address, uint64_t clock_cycle);
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};
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#endif
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@ -1,10 +1,10 @@
|
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#include "mm_model.h"
|
||||
#include "htif_phy.h"
|
||||
#include "mm_types.h"
|
||||
#include "mm_emulator.cc"
|
||||
#include "mm.h"
|
||||
#include "mm_dramsim2.h"
|
||||
#include <DirectC.h>
|
||||
|
||||
htif_phy_t* htif_phy = NULL;
|
||||
mm_t* mm = NULL;
|
||||
|
||||
extern "C" {
|
||||
|
||||
@ -23,45 +23,35 @@ void memory_tick(
|
||||
vc_handle mem_resp_tag,
|
||||
vc_handle mem_resp_data)
|
||||
{
|
||||
uint64_t req_data[MM_WORD_SIZE*refill_size/sizeof(uint64_t)];
|
||||
for (size_t i = 0; i < MM_WORD_SIZE*refill_size/sizeof(uint32_t); i++)
|
||||
((uint32_t*)req_data)[i] = vc_4stVectorRef(mem_req_data_bits)[i].d;
|
||||
uint32_t req_data[MM_WORD_SIZE*REFILL_COUNT/sizeof(uint32_t)];
|
||||
for (size_t i = 0; i < MM_WORD_SIZE*REFILL_COUNT/sizeof(uint32_t); i++)
|
||||
req_data[i] = vc_4stVectorRef(mem_req_data_bits)[i].d;
|
||||
|
||||
uint64_t req_rdy, req_data_rdy, resp_val, resp_tag;
|
||||
uint64_t resp_data[MM_WORD_SIZE*refill_size/sizeof(uint64_t)];
|
||||
vc_putScalar(mem_req_rdy, mm->req_cmd_ready());
|
||||
vc_putScalar(mem_req_data_rdy, mm->req_data_ready());
|
||||
vc_putScalar(mem_resp_val, mm->resp_valid());
|
||||
|
||||
mm_tick_emulator(
|
||||
vec32 d[MM_WORD_SIZE*REFILL_COUNT/sizeof(uint32_t)];
|
||||
d[0].c = 0;
|
||||
d[0].d = mm->resp_tag();
|
||||
vc_put4stVector(mem_resp_tag, d);
|
||||
|
||||
for (size_t i = 0; i < MM_WORD_SIZE*REFILL_COUNT/sizeof(uint32_t); i++)
|
||||
{
|
||||
d[i].c = 0;
|
||||
d[i].d = ((uint32_t*)mm->resp_data())[i];
|
||||
}
|
||||
vc_put4stVector(mem_resp_data, d);
|
||||
|
||||
mm->tick
|
||||
(
|
||||
vc_getScalar(mem_req_val),
|
||||
&req_rdy,
|
||||
vc_getScalar(mem_req_store),
|
||||
vc_4stVectorRef(mem_req_addr)->d,
|
||||
vc_4stVectorRef(mem_req_tag)->d,
|
||||
|
||||
vc_getScalar(mem_req_data_val),
|
||||
&req_data_rdy,
|
||||
req_data,
|
||||
|
||||
&resp_val,
|
||||
&resp_tag,
|
||||
resp_data
|
||||
req_data
|
||||
);
|
||||
|
||||
vc_putScalar(mem_req_rdy, req_rdy);
|
||||
vc_putScalar(mem_req_data_rdy, req_data_rdy);
|
||||
vc_putScalar(mem_resp_val, resp_val);
|
||||
|
||||
vec32 t;
|
||||
t.c = 0;
|
||||
t.d = resp_tag;
|
||||
vc_put4stVector(mem_resp_tag, &t);
|
||||
|
||||
vec32 d[MM_WORD_SIZE*refill_size/sizeof(uint32_t)];
|
||||
for (size_t i = 0; i < MM_WORD_SIZE*refill_size/sizeof(uint32_t); i++)
|
||||
{
|
||||
d[i].c = 0;
|
||||
d[i].d = ((uint32_t*)resp_data)[i];
|
||||
}
|
||||
vc_put4stVector(mem_resp_data, d);
|
||||
}
|
||||
|
||||
void htif_init
|
||||
@ -69,10 +59,12 @@ void htif_init
|
||||
vc_handle fromhost,
|
||||
vc_handle tohost,
|
||||
vc_handle width,
|
||||
vc_handle loadmem
|
||||
vc_handle loadmem,
|
||||
vc_handle dramsim
|
||||
)
|
||||
{
|
||||
uint64_t* mem = mm_init();
|
||||
mm = vc_getScalar(dramsim) ? (mm_t*)(new mm_dramsim2_t) : (mm_t*)(new mm_magic_t);
|
||||
mm->init(MEM_SIZE);
|
||||
|
||||
vec32* fh = vc_4stVectorRef(fromhost);
|
||||
vec32* th = vc_4stVectorRef(tohost);
|
||||
@ -81,7 +73,7 @@ void htif_init
|
||||
char loadmem_str[1024];
|
||||
vc_VectorToString(loadmem, loadmem_str);
|
||||
if (*loadmem_str)
|
||||
load_mem(mem, loadmem_str);
|
||||
load_mem(mm->get_data(), loadmem_str);
|
||||
|
||||
assert(w->d <= 32); // htif_tick assumes data fits in a vec32
|
||||
htif_phy = new htif_phy_t(w->d, fh->d, th->d);
|
||||
|
@ -1,18 +1,18 @@
|
||||
all: emulator
|
||||
|
||||
basedir = ..
|
||||
include ../Makefrag
|
||||
|
||||
all: emulator
|
||||
|
||||
CXX := g++
|
||||
CXXFLAGS := -O1
|
||||
CXXFLAGS := -O1 -std=c++0x
|
||||
|
||||
CXXSRCS := emulator disasm
|
||||
CXXFLAGS := $(CXXFLAGS) -Itestbench -I$(basedir)/chisel/csrc -I../dramsim2
|
||||
CXXSRCS := emulator disasm mm mm_dramsim2
|
||||
CXXFLAGS := $(CXXFLAGS) -I$(basedir)/csrc -I$(basedir)/chisel/csrc -I$(basedir)/dramsim2
|
||||
|
||||
OBJS := $(addsuffix .o,$(CXXSRCS) $(MODEL))
|
||||
DEBUG_OBJS := $(addsuffix -debug.o,$(CXXSRCS) $(MODEL))
|
||||
|
||||
CHISEL_ARGS := $(MODEL) --noIoDebug --backend c --targetDir ../emulator/generated-src
|
||||
CHISEL_ARGS := $(MODEL) --noIoDebug --backend c --targetDir $(basedir)/emulator/generated-src
|
||||
CHISEL_ARGS_DEBUG := $(CHISEL_ARGS)-debug --debug --vcd --ioDebug
|
||||
|
||||
generated-src/$(MODEL).cpp: $(basedir)/riscv-rocket/src/*.scala $(basedir)/riscv-hwacha/src/*.scala $(basedir)/chisel/src/main/scala/* $(basedir)/uncore/src/*.scala
|
||||
@ -27,18 +27,12 @@ $(MODEL).o: %.o: generated-src/%.cpp
|
||||
$(MODEL)-debug.o: %-debug.o: generated-src-debug/%.cpp
|
||||
$(CXX) $(CXXFLAGS) -Igenerated-src-debug -c -o $@ $<
|
||||
|
||||
$(addsuffix .o,$(CXXSRCS)): %.o: testbench/%.cc testbench/* generated-src/$(MODEL).cpp
|
||||
$(addsuffix .o,$(CXXSRCS)): %.o: $(basedir)/csrc/%.cc $(basedir)/csrc/*.h generated-src/$(MODEL).cpp
|
||||
$(CXX) $(CXXFLAGS) -Igenerated-src -c -o $@ $<
|
||||
|
||||
$(addsuffix -debug.o,$(CXXSRCS)): %-debug.o: testbench/%.cc testbench/* generated-src-debug/$(MODEL).cpp
|
||||
$(addsuffix -debug.o,$(CXXSRCS)): %-debug.o: $(basedir)/csrc/%.cc $(basedir)/csrc/*.h generated-src-debug/$(MODEL).cpp
|
||||
$(CXX) $(CXXFLAGS) -Igenerated-src-debug -c -o $@ $<
|
||||
|
||||
DRAMSIM_OBJS := $(patsubst %.cpp,%.o,$(wildcard ../dramsim2/*.cpp))
|
||||
$(DRAMSIM_OBJS): %.o: %.cpp
|
||||
$(CXX) $(CXXFLAGS) -DNO_STORAGE -DNO_OUTPUT -Dmain=nomain -c -o $@ $<
|
||||
libdramsim.a: $(DRAMSIM_OBJS)
|
||||
ar rcs $@ $^
|
||||
|
||||
emulator: $(OBJS) libdramsim.a
|
||||
$(CXX) $(CXXFLAGS) -o $@ $(OBJS) -L. -ldramsim
|
||||
|
||||
@ -49,7 +43,7 @@ clean:
|
||||
rm -rf *.o *.a emulator emulator-debug generated-src generated-src-debug DVEfiles output
|
||||
|
||||
test:
|
||||
cd $(basedir)/sbt && $(SBT) "project referencechip" "~make ../emulator run-fast $(CHISEL_ARGS)"
|
||||
cd $(basedir)/sbt && $(SBT) "project referencechip" "~make $(CURDIR) run-fast $(CHISEL_ARGS)"
|
||||
|
||||
#--------------------------------------------------------------------
|
||||
# Run assembly tests and benchmarks
|
||||
@ -73,13 +67,13 @@ output:
|
||||
mkdir -p $@
|
||||
|
||||
output/%.run: output/%.hex emulator
|
||||
fesvr -c -testrun -m3000000 +loadmem=$< none 2> /dev/null
|
||||
fesvr +dramsim -c -testrun -m3000000 +loadmem=$< none 2> /dev/null
|
||||
|
||||
output/%.out: output/%.hex emulator
|
||||
fesvr -c -testrun -m3000000 -l +loadmem=$< none 2> $@
|
||||
fesvr +dramsim -c -testrun -m3000000 -l +loadmem=$< none 2> $@
|
||||
|
||||
output/%.vpd: output/%.hex emulator-debug
|
||||
fesvr -c./emulator-debug -testrun -m3000000 -l -v- +loadmem=$< none 2> $(patsubst %.vpd,%.out,$@) | vcd2vpd - $@ > /dev/null && [ $$PIPESTATUS -eq 0 ]
|
||||
fesvr +dramsim -c./emulator-debug -testrun -m3000000 -l -v- +loadmem=$< none 2> $(patsubst %.vpd,%.out,$@) | vcd2vpd - $@ > /dev/null && [ $$PIPESTATUS -eq 0 ]
|
||||
|
||||
run-asm-tests: $(addprefix output/, $(addsuffix .out, $(global_asm_tests) $(global_asm_vm_tests)))
|
||||
@echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $^; echo;
|
||||
|
@ -1 +1 @@
|
||||
Subproject commit d3b86dbf35ce1ed000e95b41dd52ee24afc38351
|
||||
Subproject commit b035b2385282db65c0e700bb4b5136dc3ebcda5d
|
2
uncore
2
uncore
@ -1 +1 @@
|
||||
Subproject commit 0a991823dbc67a735cdc98e3063ec43deaf2068a
|
||||
Subproject commit 5cfbf2bce844b3fec7dd3446dbf15960aba7cb55
|
Loading…
Reference in New Issue
Block a user