riscv
/
rocket-chip
1
0
Fork 0
Code Releases Activity

refactor I$ config into RocketConfiguration

This commit is contained in:
Andrew Waterman 2012-11-04 17:00:19 -08:00
parent 4ed2d614a2
commit 0c372fc9ec
2 changed files with 3 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
riscv-rocket

@ -1 +1 @@
Subproject commit 17301fbfbd10034c61f12663d53599a8de7d00ce
Subproject commit 45d639ef571e0ba5a48c59b014d58e3de00270b2

3
src/main/scala/RocketChip.scala
View File

@ -207,7 +207,8 @@ class Top extends Component {
val hl = uncore.io.htif(i)
val tl = uncore.io.tiles(i)
implicit val rconf = RocketConfiguration(NTILES, co)
val ic = ICacheConfig(128, 2, co)
implicit val rconf = RocketConfiguration(NTILES, co, ic)
val tile = new Tile(resetSignal = hl.reset)
tile.io.host.reset := Reg(Reg(hl.reset))