Update to new privileged ISA

chisel

@@ -1 +1 @@
-Subproject commit 4483d41471e4cb8e77b61f3f13255f4d59425d61
+Subproject commit 8dc0a8e6954bc4b40e5004c451bd12020c2ae0cb

riscv-tests

@@ -1 +1 @@
-Subproject commit fdf5e6f97d53722d7ec44c4591f1ab740a092808
+Subproject commit b374fd10b2b36124bb6813211a7ec690e1fa8350

riscv-tools

@@ -1 +1 @@
-Subproject commit e5307451589e339c56e54e869bdb1d74c6cb8e90
+Subproject commit 20ff67d56c3b505b99e531d48954c2c292a2fa99

rocket

@@ -1 +1 @@
-Subproject commit 80c4fb65f40917b076576a30b574bdd4a0126251
+Subproject commit ba63ecb7cf3d2d2d871f35225ea89ba3141b8dae

src/main/scala/RocketChip.scala

@@ -157,7 +157,7 @@ class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf
     val mem_backup = new ioMemSerialized(htif_width)
     val mem_backup_en = Bool(INPUT)
   }
-  val htif = Module(new HTIF(htif_width, PCR.RESET, conf.nSCR))
+  val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR))
   val outmemsys = Module(new OuterMemorySystem(htif_width, tileList :+ htif))
   val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
   outmemsys.io.incoherent := incoherentWithHtif

src/main/scala/fpga.scala

@@ -45,7 +45,7 @@ class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit
     val htif = Vec.fill(conf.nTiles){new HTIFIO(conf.nTiles)}.flip
     val incoherent = Vec.fill(conf.nTiles){Bool()}.asInput
   }
-  val htif = Module(new HTIF(htif_width, PCR.RESET, conf.nSCR))
+  val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR))
   val outmemsys = Module(new FPGAOuterMemorySystem(htif_width, tileList :+ htif))
   val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
   outmemsys.io.incoherent := incoherentWithHtif

uncore

@@ -1 +1 @@
-Subproject commit ac4a5373c69c04a003bebe54fb7eca7387a43e4d
+Subproject commit 2a21e8435a0b58ca588bfda0ab11b54e08efe3bd