further pipeline the LLC
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914b6b622d
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@ -14,7 +14,6 @@ class BigMem[T <: Data](n: Int, readLatency: Int, leaf: Mem[Bits])(gen: => T) ex
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val wmask = gen.asInput
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val rdata = gen.asOutput
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}
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require(readLatency >= 0 && readLatency <= 2)
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val data = gen
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val colMux = if (2*data.width <= leaf.data.width && n > leaf.n) 1 << math.floor(math.log(leaf.data.width/data.width)/math.log(2)).toInt else 1
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val nWide = if (data.width > leaf.data.width) 1+(data.width-1)/leaf.data.width else 1
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@ -28,9 +27,6 @@ class BigMem[T <: Data](n: Int, readLatency: Int, leaf: Mem[Bits])(gen: => T) ex
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val cond = Vec(nDeep) { Bool() }
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val ren = Vec(nDeep) { Bool() }
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val reg_ren = Vec(nDeep) { Reg() { Bool() } }
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val reg2_ren = Vec(nDeep) { Reg() { Bool() } }
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val reg_raddr = Vec(nDeep) { Reg() { UFix() } }
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val reg2_raddr = Vec(nDeep) { Reg() { UFix() } }
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val renOut = Vec(nDeep) { Bool() }
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val raddrOut = Vec(nDeep) { UFix() }
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val rdata = Vec(nDeep) { Vec(nWide) { Bits() } }
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@ -40,11 +36,14 @@ class BigMem[T <: Data](n: Int, readLatency: Int, leaf: Mem[Bits])(gen: => T) ex
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cond(i) := (if (nDeep == 1) io.en else io.en && UFix(i) === io.addr(log2Up(n)-1, log2Up(n/nDeep)))
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ren(i) := cond(i) && !io.rw
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reg_ren(i) := ren(i)
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reg2_ren(i) := reg_ren(i)
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when (ren(i)) { reg_raddr(i) := io.addr }
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when (reg_ren(i)) { reg2_raddr(i) := reg_raddr(i) }
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renOut(i) := (if (readLatency > 1) reg2_ren(i) else if (readLatency > 0) reg_ren(i) else ren(i))
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raddrOut(i) := (if (readLatency > 1) reg2_raddr(i) else if (readLatency > 0) reg_raddr(i) else io.addr)
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renOut(i) := ren(i)
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raddrOut(i) := io.addr
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if (readLatency > 0) {
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val r = Pipe(ren(i), io.addr, readLatency)
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renOut(i) := r.valid
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raddrOut(i) := r.bits
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}
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for (j <- 0 until nWide) {
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val mem = leaf.clone
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@ -64,11 +63,8 @@ class BigMem[T <: Data](n: Int, readLatency: Int, leaf: Mem[Bits])(gen: => T) ex
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dout = mem(idx)
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} else if (readLatency == 1) {
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dout = dout1
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} else {
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val dout2 = Reg() { Bits() }
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when (reg_ren(i)) { dout2 := dout1 }
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dout = dout2
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}
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} else
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dout = Pipe(reg_ren(i), dout1, readLatency-1).bits
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rdata(i)(j) := dout
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}
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@ -238,7 +234,7 @@ class LLCWriteback(requestors: Int) extends Component
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io.mem.req_data.bits := io.data(who).bits
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}
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class LLCData(sets: Int, ways: Int, leaf: Mem[Bits]) extends Component
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class LLCData(latency: Int, sets: Int, ways: Int, leaf: Mem[Bits]) extends Component
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{
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val io = new Bundle {
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val req = (new FIFOIO) { new LLCDataReq(ways) }.flip
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@ -251,13 +247,13 @@ class LLCData(sets: Int, ways: Int, leaf: Mem[Bits]) extends Component
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val mem_resp_way = UFix(INPUT, log2Up(ways))
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}
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val data = new BigMem(sets*ways*REFILL_CYCLES, 2, leaf)(Bits(width = MEM_DATA_BITS))
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val data = new BigMem(sets*ways*REFILL_CYCLES, latency, leaf)(Bits(width = MEM_DATA_BITS))
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class QEntry extends MemResp {
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val isWriteback = Bool()
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override def clone = new QEntry().asInstanceOf[this.type]
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}
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val q = (new queue(4)) { new QEntry }
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val qReady = q.io.count <= UFix(q.entries - 3)
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val q = (new queue(latency+2)) { new QEntry }
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val qReady = q.io.count <= UFix(q.entries-latency-1)
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val valid = Reg(resetVal = Bool(false))
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val req = Reg() { io.req.bits.clone }
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val count = Reg(resetVal = UFix(0, log2Up(REFILL_CYCLES)))
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@ -287,10 +283,11 @@ class LLCData(sets: Int, ways: Int, leaf: Mem[Bits]) extends Component
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data.io.wdata := io.mem_resp.bits.data
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}
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q.io.enq.valid := Reg(Reg(data.io.en && !data.io.rw, resetVal = Bool(false)), resetVal = Bool(false))
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q.io.enq.bits.tag := Reg(Reg(Mux(valid, req.tag, io.req.bits.tag)))
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val tagPipe = Pipe(data.io.en && !data.io.rw, Mux(valid, req.tag, io.req.bits.tag), latency)
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q.io.enq.valid := tagPipe.valid
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q.io.enq.bits.tag := tagPipe.bits
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q.io.enq.bits.isWriteback := Pipe(Mux(valid, req.isWriteback, io.req.bits.isWriteback), Bool(false), latency).valid
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q.io.enq.bits.data := data.io.rdata
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q.io.enq.bits.isWriteback := Reg(Reg(Mux(valid, req.isWriteback, io.req.bits.isWriteback)))
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io.req.ready := !valid && Mux(io.req.bits.isWriteback, io.writeback.ready, Bool(true))
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io.req_data.ready := !io.mem_resp.valid && Mux(valid, req.rw, io.req.valid && io.req.bits.rw)
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@ -305,6 +302,49 @@ class LLCData(sets: Int, ways: Int, leaf: Mem[Bits]) extends Component
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io.writeback_data.bits := q.io.deq.bits
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}
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class MemReqArb(n: Int) extends Component // UNTESTED
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{
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val io = new Bundle {
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val cpu = Vec(n) { new ioMem().flip }
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val mem = new ioMem
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}
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val lock = Reg(resetVal = Bool(false))
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val locker = Reg() { UFix() }
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val arb = new RRArbiter(n)(new MemReqCmd)
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val respWho = io.mem.resp.bits.tag(log2Up(n)-1,0)
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val respTag = io.mem.resp.bits.tag >> UFix(log2Up(n))
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for (i <- 0 until n) {
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val me = UFix(i, log2Up(n))
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arb.io.in(i).valid := io.cpu(i).req_cmd.valid
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arb.io.in(i).bits := io.cpu(i).req_cmd.bits
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arb.io.in(i).bits.tag := Cat(io.cpu(i).req_cmd.bits.tag, me)
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io.cpu(i).req_cmd.ready := arb.io.in(i).ready
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io.cpu(i).req_data.ready := Bool(false)
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val getLock = io.cpu(i).req_cmd.fire() && io.cpu(i).req_cmd.bits.rw && !lock
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val haveLock = lock && locker === me
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when (getLock) {
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lock := Bool(true)
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locker := UFix(i)
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}
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when (getLock || haveLock) {
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io.cpu(i).req_data.ready := io.mem.req_data.ready
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io.mem.req_data.valid := Bool(true)
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io.mem.req_data.bits := io.cpu(i).req_data.bits
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}
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io.cpu(i).resp.valid := io.mem.resp.valid && respWho === me
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io.cpu(i).resp.bits := io.mem.resp.bits
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io.cpu(i).resp.bits.tag := respTag
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}
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io.mem.resp.ready := io.cpu(respWho).resp.ready
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val unlock = Counter(io.mem.req_data.fire(), REFILL_CYCLES)._2
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when (unlock) { lock := Bool(false) }
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}
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class DRAMSideLLC(sets: Int, ways: Int, outstanding: Int, tagLeaf: Mem[Bits], dataLeaf: Mem[Bits]) extends Component
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{
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val io = new Bundle {
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@ -319,7 +359,7 @@ class DRAMSideLLC(sets: Int, ways: Int, outstanding: Int, tagLeaf: Mem[Bits], da
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val dataArb = (new Arbiter(2)) { new LLCDataReq(ways) }
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val mshr = new LLCMSHRFile(sets, ways, outstanding)
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val tags = new BigMem(sets, 1, tagLeaf)(Bits(width = metaWidth*ways))
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val data = new LLCData(sets, ways, dataLeaf)
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val data = new LLCData(3, sets, ways, dataLeaf)
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val writeback = new LLCWriteback(2)
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val initCount = Reg(resetVal = UFix(0, log2Up(sets+1)))
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