1
0

update to new rocket; retime fpu in dc-syn

This commit is contained in:
Andrew Waterman
2012-11-04 16:43:02 -08:00
parent 538b23c223
commit 4ed2d614a2
5 changed files with 6 additions and 5 deletions

View File

@ -494,6 +494,7 @@ global_bmarks = \
vvadd.riscv \
dgemm.riscv \
dhrystone.riscv \
spmv.riscv \
global_vec_bmarkdir = $(basedir)/../../riscv-app/misc/build
global_vec_bmarks = \

2
chisel

Submodule chisel updated: bc4e7688ef...b838585734

View File

@ -156,7 +156,7 @@ int main(int argc, char** argv)
fprintf(logfile, "C: %10lld [%ld] pc=[%011lx] W[r%2ld=%016lx][%ld] R[r%2ld=%016lx] R[r%2ld=%016lx] inst=[%08lx] %-32s\n", \
(long long)trace_count, tile.Top_Tile_cpu_ctrl__wb_reg_valid.lo_word(), tile.Top_Tile_cpu_dpath__wb_reg_pc.lo_word(), \
tile.Top_Tile_cpu_dpath_rfile__io_w0_addr.lo_word(), tile.Top_Tile_cpu_dpath_rfile__io_w0_data.lo_word(), tile.Top_Tile_cpu_dpath_rfile__io_w0_en.lo_word(),
tile.Top_Tile_cpu_dpath__rf_waddr.lo_word(), tile.Top_Tile_cpu_dpath__rf_wdata.lo_word(), tile.Top_Tile_cpu_dpath__rf_wen.lo_word(),
wb_reg_raddr1, wb_reg_rs1, wb_reg_raddr2, wb_reg_rs2, wb_reg_inst, wb_inst_str);
}

View File

@ -32,7 +32,7 @@ $(addsuffix -debug.o,$(CXXSRCS)): %-debug.o: testbench/%.cc testbench/* generate
DRAMSIM_OBJS := $(patsubst %.cpp,%.o,$(wildcard ../dramsim2/*.cpp))
$(DRAMSIM_OBJS): %.o: %.cpp
$(CXX) $(CXXFLAGS) -DNO_STORAGE -Dmain=nomain -c -o $@ $<
$(CXX) $(CXXFLAGS) -DNO_STORAGE -DNO_OUTPUT -Dmain=nomain -c -o $@ $<
libdramsim.a: $(DRAMSIM_OBJS)
ar rcs $@ $^
@ -43,7 +43,7 @@ emulator-debug: $(DEBUG_OBJS) libdramsim.a
$(CXX) $(CXXFLAGS) -o $@ $(DEBUG_OBJS) -L. -ldramsim
clean:
rm -rf *.o emulator emulator-debug generated-src generated-src-debug DVEfiles output
rm -rf *.o *.a emulator emulator-debug generated-src generated-src-debug DVEfiles output
test:
cd $(basedir)/sbt && $(SBT) "project referencechip" "~make ../emulator run-fast"