update to new rocket; retime fpu in dc-syn
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parent
538b23c223
commit
4ed2d614a2
1
Makefrag
1
Makefrag
@ -494,6 +494,7 @@ global_bmarks = \
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vvadd.riscv \
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dgemm.riscv \
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dhrystone.riscv \
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spmv.riscv \
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global_vec_bmarkdir = $(basedir)/../../riscv-app/misc/build
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global_vec_bmarks = \
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2
chisel
2
chisel
@ -1 +1 @@
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Subproject commit bc4e7688efe1630c50a06aa114a4e827f367a04e
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Subproject commit b838585734ab2eb75186dca25d989bf58c018135
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@ -156,7 +156,7 @@ int main(int argc, char** argv)
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fprintf(logfile, "C: %10lld [%ld] pc=[%011lx] W[r%2ld=%016lx][%ld] R[r%2ld=%016lx] R[r%2ld=%016lx] inst=[%08lx] %-32s\n", \
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(long long)trace_count, tile.Top_Tile_cpu_ctrl__wb_reg_valid.lo_word(), tile.Top_Tile_cpu_dpath__wb_reg_pc.lo_word(), \
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tile.Top_Tile_cpu_dpath_rfile__io_w0_addr.lo_word(), tile.Top_Tile_cpu_dpath_rfile__io_w0_data.lo_word(), tile.Top_Tile_cpu_dpath_rfile__io_w0_en.lo_word(),
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tile.Top_Tile_cpu_dpath__rf_waddr.lo_word(), tile.Top_Tile_cpu_dpath__rf_wdata.lo_word(), tile.Top_Tile_cpu_dpath__rf_wen.lo_word(),
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wb_reg_raddr1, wb_reg_rs1, wb_reg_raddr2, wb_reg_rs2, wb_reg_inst, wb_inst_str);
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}
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@ -32,7 +32,7 @@ $(addsuffix -debug.o,$(CXXSRCS)): %-debug.o: testbench/%.cc testbench/* generate
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DRAMSIM_OBJS := $(patsubst %.cpp,%.o,$(wildcard ../dramsim2/*.cpp))
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$(DRAMSIM_OBJS): %.o: %.cpp
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$(CXX) $(CXXFLAGS) -DNO_STORAGE -Dmain=nomain -c -o $@ $<
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$(CXX) $(CXXFLAGS) -DNO_STORAGE -DNO_OUTPUT -Dmain=nomain -c -o $@ $<
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libdramsim.a: $(DRAMSIM_OBJS)
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ar rcs $@ $^
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@ -43,7 +43,7 @@ emulator-debug: $(DEBUG_OBJS) libdramsim.a
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$(CXX) $(CXXFLAGS) -o $@ $(DEBUG_OBJS) -L. -ldramsim
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clean:
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rm -rf *.o emulator emulator-debug generated-src generated-src-debug DVEfiles output
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rm -rf *.o *.a emulator emulator-debug generated-src generated-src-debug DVEfiles output
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test:
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cd $(basedir)/sbt && $(SBT) "project referencechip" "~make ../emulator run-fast"
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@ -1 +1 @@
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Subproject commit 12da72a5a6fcb9d33d8f3ceaedc8281c4849fd57
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Subproject commit 17301fbfbd10034c61f12663d53599a8de7d00ce
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