Andrew Waterman 7fd4eb6afd update uncore

2012-10-09 18:05:32 -07:00

chisel @ f07a7ac65c

rename hwacha -> riscv-hwacha, chisel, riscv-asm-tests-bmarks, and uncore tags

2012-10-01 19:12:18 -07:00

csrc

everything to get emulator working

2012-10-01 19:30:11 -07:00

emulator

everything to get emulator working

2012-10-01 19:30:11 -07:00

hardfloat @ eae838000e

initial commit, all the relevant submodules

2012-09-26 17:46:17 -07:00

project

reference chip design

2012-10-09 13:05:56 -07:00

riscv-rocket @ 33e042fc78

reference chip design

2012-10-09 13:05:56 -07:00

src/main/scala

reference chip design

2012-10-09 13:05:56 -07:00

uncore @ 9df53386f6

update uncore

2012-10-09 18:05:32 -07:00

.gitmodules

initial commit, all the relevant submodules

2012-09-26 17:46:17 -07:00

Makefrag

everything to get emulator working

2012-10-01 19:30:11 -07:00

sbt-launch.jar

everything to get emulator working

2012-10-01 19:30:11 -07:00

S

Description

Rocket Chip Generator (https://github.com/freechipsproject/rocket-chip)

13 MiB

0 Stars 1 Watchers 0 Forks

Languages

Scala 93.1%

C++ 2.1%

Python 2%

Makefile 1.2%

Verilog 0.8%

Other 0.7%