handle structural hazard on LLC tags
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2413763f3d
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@ -361,10 +361,10 @@ class DRAMSideLLC(sets: Int, ways: Int, outstanding: Int, tagLeaf: Mem[Bits], da
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val stall_s1 = Bool()
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val replay_s1 = Reg(resetVal = Bool(false))
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val s1_valid = Reg(io.cpu.req_cmd.valid && !stall_s1 || replay_s1, resetVal = Bool(false))
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val s1_valid = Reg(io.cpu.req_cmd.fire() || replay_s1, resetVal = Bool(false))
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replay_s1 := s1_valid && stall_s1
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val s1 = Reg() { new MemReqCmd }
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when (io.cpu.req_cmd.valid && io.cpu.req_cmd.ready) { s1 := io.cpu.req_cmd.bits }
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when (io.cpu.req_cmd.fire()) { s1 := io.cpu.req_cmd.bits }
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val stall_s2 = Bool()
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val s2_valid = Reg(resetVal = Bool(false))
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@ -430,7 +430,7 @@ class DRAMSideLLC(sets: Int, ways: Int, outstanding: Int, tagLeaf: Mem[Bits], da
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stall_s2 := s2_valid && !(dataArb.io.in(1).ready && writeback.io.req(0).ready && mshr.io.cpu.ready)
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io.cpu.resp <> data.io.resp
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io.cpu.req_cmd.ready := !stall_s1 && !replay_s1
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io.cpu.req_cmd.ready := !stall_s1 && !replay_s1 && !tag_we
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io.cpu.req_data.ready := writeback.io.data(1).ready || data.io.req_data.ready
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io.mem.req_cmd <> memCmdArb.io.out
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io.mem.req_data <> writeback.io.mem.req_data
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