Henry Cook
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dab675b231
|
refactor Metadata, clean and expand coherence API
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2014-05-28 16:05:48 -07:00 |
|
Andrew Waterman
|
4ca152b012
|
Use BundleWithConf to avoid clone method boilerplate
|
2014-05-09 19:37:16 -07:00 |
|
Henry Cook
|
5bc6981414
|
fix metadata default, add bug TODO
|
2014-05-06 18:36:22 -07:00 |
|
Henry Cook
|
7d6a642c0c
|
correct use of function value to initialize MetaDataArray
|
2014-05-06 13:00:00 -07:00 |
|
Henry Cook
|
7f690dd9c8
|
parameterize metadataarray
|
2014-05-01 01:45:45 -07:00 |
|
Henry Cook
|
519b2ea2b6
|
New metadata result trait
|
2014-04-26 19:08:56 -07:00 |
|
Henry Cook
|
1b156c6db9
|
TileLinkIO.GrantAck -> TileLinkIO.Finish
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2014-04-26 15:18:21 -07:00 |
|
Henry Cook
|
fc825c7103
|
MetaData & friends moved to uncore/
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2014-04-23 16:23:51 -07:00 |
|
Henry Cook
|
f4d326b8d7
|
Prep in HellaCache for extracting MetaData to uncore
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2014-04-23 15:43:31 -07:00 |
|
Henry Cook
|
5c62cff2ce
|
put replacement policy in uncore and minor nbdcache cleanups
|
2014-04-22 16:53:20 -07:00 |
|
Henry Cook
|
1fa505f9ff
|
remove superfluous AVec object
|
2014-04-16 17:19:32 -07:00 |
|
Henry Cook
|
1da8ef2ddf
|
Added serdes to decouple cache row size from tilelink data size
|
2014-04-10 12:34:12 -07:00 |
|
Henry Cook
|
910b3b203a
|
removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants
|
2014-04-10 12:32:44 -07:00 |
|
Henry Cook
|
ebdc0a2692
|
merge Aqcuire and AcquireData. cache line size coupled to tilelink data size
|
2014-04-10 12:09:52 -07:00 |
|
Henry Cook
|
2c2b3a7678
|
cleanups supporting uncore hierarchy
|
2014-01-31 12:07:26 -08:00 |
|
Andrew Waterman
|
57f4d89c90
|
Generate D$ replay_next signals correctly
|
2014-01-16 00:16:09 -08:00 |
|
Andrew Waterman
|
6ebdc4d94e
|
Simplify store conditional failure code generation
|
2014-01-16 00:15:48 -08:00 |
|
Andrew Waterman
|
31060ea8ae
|
Fix fubar long-latency writeback control logic
Load miss writebacks happening at the same time as multiplication
wasn't working. Hopefully this does it.
|
2014-01-14 04:02:43 -08:00 |
|
Andrew Waterman
|
e8486817e6
|
Clean up formatting (i.e. remove tabs, semicolons)
|
2014-01-13 21:43:56 -08:00 |
|
Andrew Waterman
|
07a91bb99a
|
Miscellaneous cleanup
|
2013-12-09 19:53:14 -08:00 |
|
Andrew Waterman
|
924261e2b2
|
Update to new privileged ISA... phew
|
2013-11-25 04:35:15 -08:00 |
|
Yunsup Lee
|
1583560757
|
fix replay bug, don't respond when cmd is a NOP
|
2013-10-28 22:35:18 -07:00 |
|
Andrew Waterman
|
f12bbc1e43
|
working RoCC AccumulatorExample
|
2013-09-14 22:34:53 -07:00 |
|
Andrew Waterman
|
18968dfbc7
|
Move store data generation into cache
|
2013-09-14 16:15:07 -07:00 |
|
Andrew Waterman
|
d053bdc89f
|
Remove Hwacha from Rocket
Soon it will use the coprocessor interface.
|
2013-09-12 22:34:38 -07:00 |
|
Andrew Waterman
|
59f5358435
|
Implement AQ/RL; move fence logic out of cache
|
2013-09-12 16:07:30 -07:00 |
|
Henry Cook
|
f9b85d8158
|
NetworkIOs no longer use thunks
|
2013-09-10 16:15:19 -07:00 |
|
Henry Cook
|
d06e24ac24
|
new enum syntax
|
2013-09-10 10:51:35 -07:00 |
|
Henry Cook
|
3a266cbbfa
|
final Reg changes
|
2013-08-15 15:28:15 -07:00 |
|
Henry Cook
|
b570435847
|
Reg standardization
|
2013-08-13 17:50:02 -07:00 |
|
Henry Cook
|
1a9e43aa11
|
initial attempt at upgrade
|
2013-08-12 10:39:11 -07:00 |
|
Henry Cook
|
4eaab214d2
|
Fold uncore constants into TileLinkConfiguration, update coherence API
|
2013-08-02 16:29:51 -07:00 |
|
Henry Cook
|
bef6c1db35
|
minor nbdcache cleanup
|
2013-08-02 16:29:37 -07:00 |
|
Henry Cook
|
9abdf4e154
|
Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object.
|
2013-07-23 20:27:58 -07:00 |
|
Henry Cook
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569d8fd796
|
Merge branch 'tilelink-data'
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2013-05-23 14:14:40 -07:00 |
|
Henry Cook
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69b508ff39
|
ported caches and htif to use new tilelink
|
2013-05-21 17:21:04 -07:00 |
|
Andrew Waterman
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1dab984231
|
use UFix instead of Bits for arithmetic
|
2013-05-18 00:45:29 -07:00 |
|
Andrew Waterman
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474d321cc7
|
fix meta hazard counter to reset on new meta writes
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2013-05-01 16:35:24 -07:00 |
|
Andrew Waterman
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a6a88fce19
|
Revert "broaden scope of s1_nack to include new probes accepted by the probe unit on that cycle"
This reverts commit b41e6bc50519631ba097ac1196737be7107295f9.
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2013-05-01 16:34:45 -07:00 |
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Andrew Waterman
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63a38e7982
|
Revert "temp"
This reverts commit 73705e6ed8f98d08ce6b30fbe760de694c6563ae.
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2013-05-01 16:34:33 -07:00 |
|
Henry Cook
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b6945408cb
|
temp
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2013-05-01 10:24:36 -07:00 |
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Henry Cook
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722bc917d3
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broaden scope of s1_nack to include new probes accepted by the probe unit on that cycle
|
2013-05-01 10:05:54 -07:00 |
|
Andrew Waterman
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1501e90c1f
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interlock probe unit on tag RAW hazards
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2013-04-30 00:38:22 -07:00 |
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Henry Cook
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e8b20f3d38
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clear meta state of silently-dropped, clean evictee, so as to prevent a write race on meta array between probes on evictee and refill grant
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2013-04-25 17:41:04 -07:00 |
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Andrew Waterman
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ae7720e284
|
guarantee LR/SC forward progress
the mechanism is to block new probes for several cycles after a successful LR.
this also cleans up the MSHR <-> ProbeUnit interface slightly.
|
2013-04-07 19:27:21 -07:00 |
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Andrew Waterman
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e74e032c87
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simplify MSHR memory response logic
|
2013-04-06 01:03:37 -07:00 |
|
Andrew Waterman
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1abb9277db
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fix LR/SC atomicity violation
note, it's still not starvation-free.
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2013-04-05 19:13:38 -07:00 |
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Andrew Waterman
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8cbdeb2abf
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add LR/SC support
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2013-04-04 17:07:09 -07:00 |
|
Henry Cook
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f8aebcbf8c
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fix for cache controller bug: failing to mux correct metadata into mshr.io.old_meta on tag match
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2013-04-04 15:50:29 -07:00 |
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Henry Cook
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95f0a688e9
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Merge branch 'release-xacts'
Conflicts:
src/htif.scala
src/icache.scala
src/nbdcache.scala
src/tile.scala
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2013-03-20 17:37:50 -07:00 |
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Henry Cook
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273bd34091
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Generalized mem arbiter, moved to uncore. Support for multiple banks when acking grants.
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2013-03-20 15:53:36 -07:00 |
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Andrew Waterman
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ea9d0b771e
|
remove aborts; simplify probes
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2013-03-19 15:29:40 -07:00 |
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Henry Cook
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e0361840bd
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writebacks on release network pass asm tests and bmarks
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2013-02-28 18:11:40 -08:00 |
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Andrew Waterman
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35349d227f
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update to new Mem style
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2013-02-20 16:09:46 -08:00 |
|
Andrew Waterman
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1fbc20450e
|
don't allow simultaneous reads and writes to the tag ram
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2013-01-24 17:55:00 -08:00 |
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Andrew Waterman
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37ee843b2c
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don't use reset combinationally
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2013-01-24 17:55:00 -08:00 |
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Andrew Waterman
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bb6fbddf1f
|
don't probe the mshr file to inquire about refills
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2013-01-24 17:54:59 -08:00 |
|
Rimas Avizienis
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63060bc0a8
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minor tweaks for eos18 tapeout (SRAM r/w port ordering, etc)
|
2013-01-23 19:27:53 -08:00 |
|
Henry Cook
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6b00e7ff74
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New TileLink bundle names
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2013-01-21 17:18:23 -08:00 |
|
Henry Cook
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a2fa3fd04d
|
Refactored packet headers/payloads
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2013-01-15 15:50:37 -08:00 |
|
Henry Cook
|
e1225c5114
|
standardize IO naming convention
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2013-01-07 13:41:36 -08:00 |
|
Henry Cook
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261e14f831
|
Refactored uncore conf
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2013-01-07 13:41:36 -08:00 |
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Andrew Waterman
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f5c53ce35d
|
add ecc support to d$ data rams
i haven't injected errors yet; it may well be incorrect.
|
2012-12-11 15:58:53 -08:00 |
|
Andrew Waterman
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3f59e439ef
|
fix d$ tag raw hazard
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2012-12-07 15:14:20 -08:00 |
|
Andrew Waterman
|
4dda38204f
|
fix d$ reset bug
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2012-12-06 03:13:22 -08:00 |
|
Andrew Waterman
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290d3d226c
|
fix AMO and store bypass bugs
thanks, torture tester
|
2012-12-06 02:07:52 -08:00 |
|
Andrew Waterman
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4608660f6e
|
torture revealed a couple bugs
FP loads/stores with certain negative offsets could cause illegal rounding
mode traps, and x's were cropping up in situations that are benign in HW.
|
2012-12-04 05:57:53 -08:00 |
|
Andrew Waterman
|
90cae54ac4
|
fix D$ read/write concurrency bug
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2012-11-27 02:42:27 -08:00 |
|
Andrew Waterman
|
608f65e716
|
don't wastefully read 2x the bits from D$ RAMs
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2012-11-26 20:34:30 -08:00 |
|
Andrew Waterman
|
8a6ff5f9aa
|
fix D$ writeback bug
I swear I did this last week... perhaps I am finally losing it!
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2012-11-25 19:46:48 -08:00 |
|
Andrew Waterman
|
de2f28193a
|
get rid of more global constants
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2012-11-25 04:24:25 -08:00 |
|
Andrew Waterman
|
c036cdc1ea
|
add option for 2-cycle load-use delay
|
2012-11-24 22:01:08 -08:00 |
|
Andrew Waterman
|
2b26082132
|
use 1r1w ram for tags; merge tags & permissions
setting the dirty bit now allocates an MSHR (to reuse the existing datapath)
|
2012-11-20 04:09:26 -08:00 |
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Andrew Waterman
|
30038bda8a
|
bypass stores to subsequent loads
since we handle subword stores as RMW operations, this occurs frequently
|
2012-11-20 01:33:32 -08:00 |
|
Yunsup Lee
|
395e4e3dd6
|
andrew'x fix for D$ corner case in writeback->abort->probe
|
2012-11-18 03:11:06 -08:00 |
|
Yunsup Lee
|
81d711e892
|
fix D$ bug; now D$ doesn't respond to prefetches
|
2012-11-17 20:06:13 -08:00 |
|
Andrew Waterman
|
29bc361d6c
|
remove global constants; disentangle hwacha a bit
|
2012-11-17 17:24:08 -08:00 |
|
Andrew Waterman
|
e68b039133
|
fix misc. D$ control bugs
|
2012-11-17 06:47:27 -08:00 |
|
Andrew Waterman
|
dad7b71062
|
provide cmd/addr with cache response
|
2012-11-16 21:26:12 -08:00 |
|
Andrew Waterman
|
cb8ac73045
|
provide store data with cache response
|
2012-11-16 21:15:13 -08:00 |
|
Andrew Waterman
|
9e010beffe
|
fix D$ refill bug
|
2012-11-16 21:05:29 -08:00 |
|
Andrew Waterman
|
8dce89703a
|
new D$ with better QoR and AMO pipelining
Vector unit is disabled because nack handling needs to be fixed.
|
2012-11-16 02:39:33 -08:00 |
|
Andrew Waterman
|
6d10115b19
|
fix D$ tag width
|
2012-11-15 16:46:39 -08:00 |
|
Yunsup Lee
|
9a02298f6f
|
andrew's fix for tlb lockup
|
2012-11-06 23:52:58 -08:00 |
|
Andrew Waterman
|
4d1ca8ba3a
|
remove more global consts; refactor DTLBs
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
|
2012-11-06 08:13:44 -08:00 |
|
Andrew Waterman
|
c5b93798fb
|
factor out more global constants
|
2012-11-05 23:52:32 -08:00 |
|
Henry Cook
|
88ac5af181
|
Merged consts-as-traits
|
2012-10-16 16:32:35 -07:00 |
|
Andrew Waterman
|
fc648d13a1
|
remove old Mux1H; add implicit conversions
|
2012-10-16 02:24:37 -07:00 |
|
Henry Cook
|
8970b635b2
|
improvements to implicit RocketConfiguration parameter
|
2012-10-15 16:29:49 -07:00 |
|
Henry Cook
|
9025d0610c
|
first pass at configuration object passed as implicit parameter
|
2012-10-07 22:37:29 -07:00 |
|
Andrew Waterman
|
ed8cc4a1cf
|
eliminate D$ probe->WB critical path
|
2012-10-04 09:05:14 -07:00 |
|
Huy Vo
|
e909093f37
|
factoring out uncore into separate uncore repo
|
2012-10-01 16:08:41 -07:00 |
|
Henry Cook
|
b9a9664de5
|
uncore and rocket changes for new xact types
|
2012-10-01 10:47:36 -07:00 |
|
Andrew Waterman
|
0f20771664
|
rename queue to Queue
fixes build with case-insensitive file system
|
2012-08-08 22:11:59 -07:00 |
|
Andrew Waterman
|
938effc053
|
don't dequeue probe queue during reset
|
2012-07-22 21:05:52 -07:00 |
|
Yunsup Lee
|
f633a55722
|
fix dcache tag array size
|
2012-07-16 22:19:03 -07:00 |
|
Huy Vo
|
fd95159837
|
INPUT/OUTPUT orderring swapped
|
2012-07-12 18:16:57 -07:00 |
|
Andrew Waterman
|
bac82762d3
|
use only one (wide) tag ram for set assoc. caches
|
2012-07-12 14:50:12 -07:00 |
|
Andrew Waterman
|
4e5f874266
|
update to new chisel/hwacha
|
2012-06-08 00:13:14 -07:00 |
|
Huy Vo
|
a99cebb483
|
ioDecoupled -> FIFOIO, ioPipe -> PipeIO
|
2012-06-06 18:22:56 -07:00 |
|