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ioDecoupled -> FIFOIO, ioPipe -> PipeIO

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This commit is contained in:
Huy Vo 2012-06-06 18:22:56 -07:00
parent 04304fe788
commit a99cebb483
9 changed files with 86 additions and 86 deletions
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8
rocket/src/main/scala/arbiter.scala
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@ -5,10 +5,10 @@ import Node._;
import Constants._;
class ioUncachedRequestor extends Bundle {
val xact_init = (new ioDecoupled) { new TransactionInit }
val xact_abort = (new ioDecoupled) { new TransactionAbort }.flip
val xact_rep = (new ioPipe) { new TransactionReply }.flip
val xact_finish = (new ioDecoupled) { new TransactionFinish }
val xact_init = (new FIFOIO) { new TransactionInit }
val xact_abort = (new FIFOIO) { new TransactionAbort }.flip
val xact_rep = (new PipeIO) { new TransactionReply }.flip
val xact_finish = (new FIFOIO) { new TransactionFinish }
}
class rocketMemArbiter(n: Int) extends Component {

2
rocket/src/main/scala/dtlb.scala
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@ -17,7 +17,7 @@ class ioDTLB_CPU_req_bundle extends Bundle
val asid = Bits(width=ASID_BITS)
val vpn = Bits(width=VPN_BITS+1)
}
class ioDTLB_CPU_req extends ioDecoupled()( { new ioDTLB_CPU_req_bundle() } )
class ioDTLB_CPU_req extends FIFOIO()( { new ioDTLB_CPU_req_bundle() } )
class ioDTLB_CPU_resp extends Bundle
{

10
rocket/src/main/scala/htif.scala
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@ -11,8 +11,8 @@ class ioDebug extends Bundle
class ioHost(w: Int) extends Bundle
{
val in = new ioDecoupled()(Bits(width = w)).flip
val out = new ioDecoupled()(Bits(width = w))
val in = new FIFOIO()(Bits(width = w)).flip
val out = new FIFOIO()(Bits(width = w))
}
class PCRReq extends Bundle
@ -26,9 +26,9 @@ class ioHTIF extends Bundle
{
val reset = Bool(INPUT)
val debug = new ioDebug
val pcr_req = (new ioDecoupled) { new PCRReq }.flip
val pcr_rep = (new ioPipe) { Bits(width = 64) }
val ipi = (new ioDecoupled) { Bits(width = log2Up(NTILES)) }
val pcr_req = (new FIFOIO) { new PCRReq }.flip
val pcr_rep = (new PipeIO) { Bits(width = 64) }
val ipi = (new FIFOIO) { Bits(width = log2Up(NTILES)) }
}
class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends Component

4
rocket/src/main/scala/memserdes.scala
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@ -7,8 +7,8 @@ import scala.math._
class ioMemSerialized extends Bundle
{
val req = (new ioDecoupled) { Bits(width = MEM_BACKUP_WIDTH) }
val resp = (new ioPipe) { Bits(width = MEM_BACKUP_WIDTH) }.flip
val req = (new FIFOIO) { Bits(width = MEM_BACKUP_WIDTH) }
val resp = (new PipeIO) { Bits(width = MEM_BACKUP_WIDTH) }.flip
}
class MemSerdes extends Component

80
rocket/src/main/scala/nbdcache.scala
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@ -173,15 +173,15 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component {
val tag = Bits(TAG_BITS, OUTPUT)
val way_oh = Bits(NWAYS, OUTPUT)
val mem_req = (new ioDecoupled) { new TransactionInit }
val meta_req = (new ioDecoupled) { new MetaArrayReq() }
val replay = (new ioDecoupled) { new Replay() }
val mem_abort = (new ioPipe) { new TransactionAbort }.flip
val mem_rep = (new ioPipe) { new TransactionReply }.flip
val mem_finish = (new ioDecoupled) { new TransactionFinish }
val wb_req = (new ioDecoupled) { new WritebackReq }
val probe_writeback = (new ioDecoupled) { Bool() }.flip
val probe_refill = (new ioDecoupled) { Bool() }.flip
val mem_req = (new FIFOIO) { new TransactionInit }
val meta_req = (new FIFOIO) { new MetaArrayReq() }
val replay = (new FIFOIO) { new Replay() }
val mem_abort = (new PipeIO) { new TransactionAbort }.flip
val mem_rep = (new PipeIO) { new TransactionReply }.flip
val mem_finish = (new FIFOIO) { new TransactionFinish }
val wb_req = (new FIFOIO) { new WritebackReq }
val probe_writeback = (new FIFOIO) { Bool() }.flip
val probe_refill = (new FIFOIO) { Bool() }.flip
}
val s_invalid :: s_wb_req :: s_wb_resp :: s_meta_clear :: s_refill_req :: s_refill_resp :: s_drain_rpq :: Nil = Enum(7) { UFix() }
@ -294,7 +294,7 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component {
class MSHRFile(co: CoherencePolicy) extends Component {
val io = new Bundle {
val req = (new ioDecoupled) { new MSHRReq }.flip
val req = (new FIFOIO) { new MSHRReq }.flip
val secondary_miss = Bool(OUTPUT)
val mem_resp_idx = Bits(IDX_BITS, OUTPUT)
@ -303,14 +303,14 @@ class MSHRFile(co: CoherencePolicy) extends Component {
val fence_rdy = Bool(OUTPUT)
val mem_req = (new ioDecoupled) { new TransactionInit }
val meta_req = (new ioDecoupled) { new MetaArrayReq() }
val data_req = (new ioDecoupled) { new DataReq() }
val mem_abort = (new ioPipe) { new TransactionAbort }.flip
val mem_rep = (new ioPipe) { new TransactionReply }.flip
val mem_finish = (new ioDecoupled) { new TransactionFinish }
val wb_req = (new ioDecoupled) { new WritebackReq }
val probe = (new ioDecoupled) { Bool() }.flip
val mem_req = (new FIFOIO) { new TransactionInit }
val meta_req = (new FIFOIO) { new MetaArrayReq() }
val data_req = (new FIFOIO) { new DataReq() }
val mem_abort = (new PipeIO) { new TransactionAbort }.flip
val mem_rep = (new PipeIO) { new TransactionReply }.flip
val mem_finish = (new FIFOIO) { new TransactionFinish }
val wb_req = (new FIFOIO) { new WritebackReq }
val probe = (new FIFOIO) { Bool() }.flip
val cpu_resp_val = Bool(OUTPUT)
val cpu_resp_tag = Bits(DCACHE_TAG_BITS, OUTPUT)
@ -416,13 +416,13 @@ class MSHRFile(co: CoherencePolicy) extends Component {
class WritebackUnit(co: CoherencePolicy) extends Component {
val io = new Bundle {
val req = (new ioDecoupled) { new WritebackReq() }.flip
val probe = (new ioDecoupled) { new WritebackReq() }.flip
val data_req = (new ioDecoupled) { new DataArrayReq() }
val req = (new FIFOIO) { new WritebackReq() }.flip
val probe = (new FIFOIO) { new WritebackReq() }.flip
val data_req = (new FIFOIO) { new DataArrayReq() }
val data_resp = Bits(MEM_DATA_BITS, INPUT)
val mem_req = (new ioDecoupled) { new TransactionInit }
val mem_req_data = (new ioDecoupled) { new TransactionInitData }
val probe_rep_data = (new ioDecoupled) { new ProbeReplyData }
val mem_req = (new FIFOIO) { new TransactionInit }
val mem_req_data = (new FIFOIO) { new TransactionInitData }
val probe_rep_data = (new FIFOIO) { new ProbeReplyData }
}
val valid = Reg(resetVal = Bool(false))
@ -485,11 +485,11 @@ class WritebackUnit(co: CoherencePolicy) extends Component {
class ProbeUnit(co: CoherencePolicy) extends Component {
val io = new Bundle {
val req = (new ioDecoupled) { new ProbeRequest }.flip
val rep = (new ioDecoupled) { new ProbeReply }
val meta_req = (new ioDecoupled) { new MetaArrayReq }
val mshr_req = (new ioDecoupled) { Bool() }
val wb_req = (new ioDecoupled) { new WritebackReq }
val req = (new FIFOIO) { new ProbeRequest }.flip
val rep = (new FIFOIO) { new ProbeReply }
val meta_req = (new FIFOIO) { new MetaArrayReq }
val mshr_req = (new FIFOIO) { Bool() }
val wb_req = (new FIFOIO) { new WritebackReq }
val tag_match_way_oh = Bits(NWAYS, INPUT)
val line_state = UFix(2, INPUT)
val address = Bits(PADDR_BITS-OFFSET_BITS, OUTPUT)
@ -548,9 +548,9 @@ class ProbeUnit(co: CoherencePolicy) extends Component {
class FlushUnit(lines: Int, co: CoherencePolicy) extends Component {
val io = new Bundle {
val req = (new ioDecoupled) { Bool() }.flip
val meta_req = (new ioDecoupled) { new MetaArrayReq() }
val mshr_req = (new ioDecoupled) { Bool() }
val req = (new FIFOIO) { Bool() }.flip
val meta_req = (new FIFOIO) { new MetaArrayReq() }
val mshr_req = (new FIFOIO) { Bool() }
}
val s_reset :: s_ready :: s_meta_read :: s_meta_wait :: Nil = Enum(4) { UFix() }
@ -597,9 +597,9 @@ class FlushUnit(lines: Int, co: CoherencePolicy) extends Component {
class MetaDataArray(lines: Int) extends Component {
val io = new Bundle {
val req = (new ioDecoupled) { new MetaArrayReq() }.flip
val req = (new FIFOIO) { new MetaArrayReq() }.flip
val resp = (new MetaData).asOutput()
val state_req = (new ioDecoupled) { new MetaArrayReq() }.flip
val state_req = (new FIFOIO) { new MetaArrayReq() }.flip
}
val permissions_array = Mem(lines){ UFix(width = 2) }
@ -626,9 +626,9 @@ class MetaDataArray(lines: Int) extends Component {
class MetaDataArrayArray(lines: Int) extends Component {
val io = new Bundle {
val req = (new ioDecoupled) { new MetaArrayReq() }.flip
val req = (new FIFOIO) { new MetaArrayReq() }.flip
val resp = Vec(NWAYS){ (new MetaData).asOutput }
val state_req = (new ioDecoupled) { new MetaArrayReq() }.flip
val state_req = (new FIFOIO) { new MetaArrayReq() }.flip
val way_en = Bits(width = NWAYS, dir = OUTPUT)
}
@ -653,7 +653,7 @@ class MetaDataArrayArray(lines: Int) extends Component {
class DataArray(lines: Int) extends Component {
val io = new Bundle {
val req = (new ioDecoupled) { new DataArrayReq() }.flip
val req = (new FIFOIO) { new DataArrayReq() }.flip
val resp = Bits(width = MEM_DATA_BITS, dir = OUTPUT)
}
@ -673,7 +673,7 @@ class DataArray(lines: Int) extends Component {
class DataArrayArray(lines: Int) extends Component {
val io = new Bundle {
val req = (new ioDecoupled) { new DataArrayReq() }.flip
val req = (new FIFOIO) { new DataArrayReq() }.flip
val resp = Vec(NWAYS){ Bits(width = MEM_DATA_BITS, dir = OUTPUT) }
val way_en = Bits(width = NWAYS, dir = OUTPUT)
}
@ -756,8 +756,8 @@ class HellaCacheExceptions extends Bundle {
// interface between D$ and processor/DTLB
class ioHellaCache extends Bundle {
val req = (new ioDecoupled){ new HellaCacheReq }
val resp = (new ioPipe){ new HellaCacheResp }.flip
val req = (new FIFOIO){ new HellaCacheReq }
val resp = (new PipeIO){ new HellaCacheResp }.flip
val xcpt = (new HellaCacheExceptions).asInput
}

12
rocket/src/main/scala/queues.scala
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@ -6,8 +6,8 @@ import Node._;
class ioQueue[T <: Data](flushable: Boolean)(data: => T) extends Bundle
{
val flush = if (flushable) Bool(INPUT) else null
val enq = new ioDecoupled()(data).flip
val deq = new ioDecoupled()(data)
val enq = new FIFOIO()(data).flip
val deq = new FIFOIO()(data)
}
class queue[T <: Data](entries: Int, pipe: Boolean = false, flushable: Boolean = false)(data: => T) extends Component
@ -60,7 +60,7 @@ class queue[T <: Data](entries: Int, pipe: Boolean = false, flushable: Boolean =
object Queue
{
def apply[T <: Data](enq: ioDecoupled[T], entries: Int = 2, pipe: Boolean = false) = {
def apply[T <: Data](enq: FIFOIO[T], entries: Int = 2, pipe: Boolean = false) = {
val q = (new queue(entries, pipe)) { enq.bits.clone }
q.io.enq <> enq
q.io.deq
@ -70,8 +70,8 @@ object Queue
class pipereg[T <: Data]()(data: => T) extends Component
{
val io = new Bundle {
val enq = new ioPipe()(data).flip
val deq = new ioPipe()(data)
val enq = new PipeIO()(data).flip
val deq = new PipeIO()(data)
}
//val bits = Reg() { io.enq.bits.clone }
@ -88,7 +88,7 @@ class pipereg[T <: Data]()(data: => T) extends Component
object Pipe
{
def apply[T <: Data](enq: ioPipe[T], latency: Int = 1): ioPipe[T] = {
def apply[T <: Data](enq: PipeIO[T], latency: Int = 1): PipeIO[T] = {
val q = (new pipereg) { enq.bits.clone }
q.io.enq <> enq
q.io.deq

8
rocket/src/main/scala/slowio.scala
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@ -6,11 +6,11 @@ import Constants._
class slowIO[T <: Data](val divisor: Int, hold_cycles_in: Int = -1)(data: => T) extends Component
{
val io = new Bundle {
val out_fast = new ioDecoupled()(data).flip
val out_slow = new ioDecoupled()(data)
val out_fast = new FIFOIO()(data).flip
val out_slow = new FIFOIO()(data)
val in_fast = new ioDecoupled()(data)
val in_slow = new ioDecoupled()(data).flip
val in_fast = new FIFOIO()(data)
val in_slow = new FIFOIO()(data).flip
val clk_slow = Bool(OUTPUT)
}

44
rocket/src/main/scala/uncore.scala
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@ -21,9 +21,9 @@ class MemResp () extends MemData
class ioMem() extends Bundle
{
val req_cmd = (new ioDecoupled) { new MemReqCmd() }
val req_data = (new ioDecoupled) { new MemData() }
val resp = (new ioPipe) { new MemResp() }.flip
val req_cmd = (new FIFOIO) { new MemReqCmd() }
val req_data = (new FIFOIO) { new MemData() }
val resp = (new PipeIO) { new MemResp() }.flip
}
class TrackerProbeData extends Bundle {
@ -40,34 +40,34 @@ class TrackerDependency extends Bundle {
}
class ioTileLink extends Bundle {
val xact_init = (new ioDecoupled) { new TransactionInit }
val xact_init_data = (new ioDecoupled) { new TransactionInitData }
val xact_abort = (new ioDecoupled) { new TransactionAbort }.flip
val probe_req = (new ioDecoupled) { new ProbeRequest }.flip
val probe_rep = (new ioDecoupled) { new ProbeReply }
val probe_rep_data = (new ioDecoupled) { new ProbeReplyData }
val xact_rep = (new ioPipe) { new TransactionReply }.flip
val xact_finish = (new ioDecoupled) { new TransactionFinish }
val xact_init = (new FIFOIO) { new TransactionInit }
val xact_init_data = (new FIFOIO) { new TransactionInitData }
val xact_abort = (new FIFOIO) { new TransactionAbort }.flip
val probe_req = (new FIFOIO) { new ProbeRequest }.flip
val probe_rep = (new FIFOIO) { new ProbeReply }
val probe_rep_data = (new FIFOIO) { new ProbeReplyData }
val xact_rep = (new PipeIO) { new TransactionReply }.flip
val xact_finish = (new FIFOIO) { new TransactionFinish }
}
class XactTracker(ntiles: Int, id: Int, co: CoherencePolicy) extends Component {
val io = new Bundle {
val alloc_req = (new ioDecoupled) { new TrackerAllocReq }.flip
val p_data = (new ioPipe) { new TrackerProbeData }.flip
val alloc_req = (new FIFOIO) { new TrackerAllocReq }.flip
val p_data = (new PipeIO) { new TrackerProbeData }.flip
val can_alloc = Bool(INPUT)
val xact_finish = Bool(INPUT)
val p_rep_cnt_dec = Bits(ntiles, INPUT)
val p_req_cnt_inc = Bits(ntiles, INPUT)
val p_rep_data = (new ioPipe) { new ProbeReplyData }.flip
val x_init_data = (new ioPipe) { new TransactionInitData }.flip
val p_rep_data = (new PipeIO) { new ProbeReplyData }.flip
val x_init_data = (new PipeIO) { new TransactionInitData }.flip
val sent_x_rep_ack = Bool(INPUT)
val p_rep_data_dep = (new ioPipe) { new TrackerDependency }.flip
val x_init_data_dep = (new ioPipe) { new TrackerDependency }.flip
val p_rep_data_dep = (new PipeIO) { new TrackerDependency }.flip
val x_init_data_dep = (new PipeIO) { new TrackerDependency }.flip
val mem_req_cmd = (new ioDecoupled) { new MemReqCmd }
val mem_req_data = (new ioDecoupled) { new MemData }
val mem_req_cmd = (new FIFOIO) { new MemReqCmd }
val mem_req_data = (new FIFOIO) { new MemData }
val mem_req_lock = Bool(OUTPUT)
val probe_req = (new ioDecoupled) { new ProbeRequest }
val probe_req = (new FIFOIO) { new ProbeRequest }
val busy = Bool(OUTPUT)
val addr = Bits(PADDR_BITS - OFFSET_BITS, OUTPUT)
val init_tile_id = Bits(TILE_ID_BITS, OUTPUT)
@ -85,7 +85,7 @@ class XactTracker(ntiles: Int, id: Int, co: CoherencePolicy) extends Component {
val send_x_rep_ack = Bool(OUTPUT)
}
def doMemReqWrite(req_cmd: ioDecoupled[MemReqCmd], req_data: ioDecoupled[MemData], lock: Bool, data: ioPipe[MemData], trigger: Bool, cmd_sent: Bool, pop_data: Bits, pop_dep: Bits, at_front_of_dep_queue: Bool, tile_id: UFix) {
def doMemReqWrite(req_cmd: FIFOIO[MemReqCmd], req_data: FIFOIO[MemData], lock: Bool, data: PipeIO[MemData], trigger: Bool, cmd_sent: Bool, pop_data: Bits, pop_dep: Bits, at_front_of_dep_queue: Bool, tile_id: UFix) {
req_cmd.valid := !cmd_sent && data.valid && at_front_of_dep_queue
req_cmd.bits.rw := Bool(true)
req_data.valid := data.valid && at_front_of_dep_queue
@ -106,7 +106,7 @@ class XactTracker(ntiles: Int, id: Int, co: CoherencePolicy) extends Component {
}
}
def doMemReqRead(req_cmd: ioDecoupled[MemReqCmd], trigger: Bool) {
def doMemReqRead(req_cmd: FIFOIO[MemReqCmd], trigger: Bool) {
req_cmd.valid := Bool(true)
req_cmd.bits.rw := Bool(false)
when(req_cmd.ready) {

4
rocket/src/main/scala/util.scala
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@ -27,9 +27,9 @@ class Mux1H [T <: Data](n: Int)(gen: => T) extends Component
}
class ioLockingArbiter[T <: Data](n: Int)(data: => T) extends Bundle {
val in = Vec(n) { (new ioDecoupled()) { data } }.flip
val in = Vec(n) { (new FIFOIO()) { data } }.flip
val lock = Vec(n) { Bool() }.asInput
val out = (new ioDecoupled()) { data }
val out = (new FIFOIO()) { data }
}
class LockingArbiter[T <: Data](n: Int)(data: => T) extends Component {