interlock probe unit on tag RAW hazards
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@ -283,7 +283,10 @@ class MSHR(id: Int)(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfigura
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io.tag := req.addr >> conf.untagbits
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io.req_pri_rdy := state === s_invalid
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io.req_sec_rdy := sec_rdy && rpq.io.enq.ready
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io.probe_rdy := !idx_match || (state != s_wb_req && state != s_wb_resp && state != s_meta_clear)
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val meta_hazard = Reg(resetVal = UFix(0,2))
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when (meta_hazard != 0 || io.meta_write.fire()) { meta_hazard := meta_hazard + 1 }
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io.probe_rdy := !idx_match || (state != s_wb_req && state != s_wb_resp && state != s_meta_clear && meta_hazard === 0)
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io.meta_write.valid := state === s_meta_write_req || state === s_meta_clear
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io.meta_write.bits.idx := req_idx
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