fix LR/SC atomicity violation
note, it's still not starvation-free.
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8cbdeb2abf
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@ -872,8 +872,10 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio
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// load-reserved/store-conditional
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val s2_lr_valid = Reg(resetVal = Bool(false))
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val s2_lr_addr = Reg{UFix()}
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val s2_lr_addr_match = s2_lr_addr === (s2_req.addr >> conf.offbits)
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when (s2_valid_masked && s2_req.cmd === M_XLR) {
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val (s2_lr, s2_sc) = (s2_req.cmd === M_XLR, s2_req.cmd === M_XSC)
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val s2_lr_addr_match = s2_lr_valid && s2_lr_addr === (s2_req.addr >> conf.offbits)
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val s2_sc_fail = s2_sc && !s2_lr_addr_match
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when ((s2_valid_masked && s2_hit || s2_replay) && s2_lr) {
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s2_lr_valid := true
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s2_lr_addr := s2_req.addr >> conf.offbits
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}
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@ -898,7 +900,7 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio
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val s2_data_correctable = AVec(s2_data_decoded.map(_.correctable)).toBits()(s2_word_idx)
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// store/amo hits
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s3_valid := (s2_valid_masked && s2_hit || s2_replay) && isWrite(s2_req.cmd)
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s3_valid := (s2_valid_masked && s2_hit && !s2_sc_fail || s2_replay) && isWrite(s2_req.cmd)
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val amoalu = new AMOALU
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when ((s2_valid || s2_replay) && (isWrite(s2_req.cmd) || s2_data_correctable)) {
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s3_req := s2_req
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@ -978,7 +980,7 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio
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val s4_valid = Reg(s3_valid, resetVal = Bool(false))
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val s4_req = RegEn(s3_req, s3_valid && metaReadArb.io.out.valid)
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val bypasses = List(
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(s2_valid_masked || s2_replay, s2_req, amoalu.io.out),
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(s2_valid_masked && !s2_sc_fail || s2_replay, s2_req, amoalu.io.out),
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(s3_valid, s3_req, s3_req.data),
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(s4_valid, s4_req, s4_req.data)
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).map(r => (r._1 && (s1_addr >> conf.wordoffbits === r._2.addr >> conf.wordoffbits) && isWrite(r._2.cmd), r._3))
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@ -1026,13 +1028,13 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio
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io.cpu.req.ready := Bool(false)
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}
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val s2_read = isRead(s2_req.cmd) || s2_req.cmd === M_XSC
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io.cpu.resp.valid := s2_read && (s2_replay || s2_valid_masked && s2_hit) && !s2_data_correctable
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val s2_do_resp = isRead(s2_req.cmd) || s2_sc
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io.cpu.resp.valid := s2_do_resp && (s2_replay || s2_valid_masked && s2_hit) && !s2_data_correctable
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io.cpu.resp.bits.nack := s2_valid && s2_nack
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io.cpu.resp.bits := s2_req
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io.cpu.resp.bits.replay := s2_replay && s2_read
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io.cpu.resp.bits.replay := s2_replay && s2_do_resp
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io.cpu.resp.bits.data := loadgen.word
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io.cpu.resp.bits.data_subword := Mux(s2_req.cmd === M_XSC, !s2_lr_addr_match, loadgen.byte)
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io.cpu.resp.bits.data_subword := Mux(s2_sc, s2_sc_fail, loadgen.byte)
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io.cpu.resp.bits.store_data := s2_req.data
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io.mem.grant_ack <> mshr.io.mem_finish
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