don't probe the mshr file to inquire about refills
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5b9f938263
commit
bb6fbddf1f
@ -175,7 +175,6 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component {
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val mem_finish = (new FIFOIO) { new GrantAck }
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val wb_req = (new FIFOIO) { new WritebackReq }
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val probe_writeback = (new FIFOIO) { Bool() }.flip
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val probe_refill = (new FIFOIO) { Bool() }.flip
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}
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val s_invalid :: s_wb_req :: s_wb_resp :: s_meta_clear :: s_refill_req :: s_refill_resp :: s_meta_write_req :: s_meta_write_resp :: s_drain_rpq :: Nil = Enum(9) { UFix() }
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@ -185,6 +184,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component {
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val line_state = Reg { UFix() }
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val refill_count = Reg { UFix(width = log2Up(REFILL_CYCLES)) }
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val req = Reg { new MSHRReq() }
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val writeback_probed = Reg{Bool()}
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val req_cmd = io.req_bits.cmd
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val req_idx = req.addr(conf.untagbits-1,conf.offbits)
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@ -202,12 +202,13 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component {
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val refill_done = reply && refill_count.andR
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val wb_done = reply && (state === s_wb_resp)
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val finish_q = (new Queue(2 /* wb + refill */)) { new GrantAck }
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finish_q.io.enq.valid := wb_done || refill_done
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finish_q.io.enq.bits.master_xact_id := io.mem_rep.bits.master_xact_id
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io.wb_req.valid := Bool(false)
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when (io.probe_writeback.valid && idx_match && io.probe_writeback.bits) {
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writeback_probed := true
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}
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io.probe_writeback.ready := !idx_match || state != s_wb_req && state != s_wb_resp && state != s_meta_clear
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when (state === s_drain_rpq && !rpq.io.deq.valid && !finish_q.io.deq.valid) {
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when (state === s_drain_rpq && !rpq.io.deq.valid) {
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state := s_invalid
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}
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when (state === s_meta_write_resp) {
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@ -234,24 +235,25 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component {
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}
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when (state === s_wb_resp) {
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when (reply) { state := s_meta_clear }
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when (abort) { state := s_wb_req }
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when (abort) { state := Mux(writeback_probed, s_refill_req, s_wb_req) }
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}
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when (state === s_wb_req) {
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io.wb_req.valid := Bool(true)
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when (io.probe_writeback.valid && idx_match) {
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io.wb_req.valid := Bool(false)
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when (io.probe_writeback.bits) { state := s_refill_req }
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io.wb_req.valid := true
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when (writeback_probed) {
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io.wb_req.valid := false
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state := s_refill_req
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}.elsewhen (io.wb_req.ready) { state := s_wb_resp }
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}
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when (io.req_sec_val && io.req_sec_rdy) { // s_wb_req, s_wb_resp, s_refill_req
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acq_type := conf.co.getAcquireTypeOnSecondaryMiss(req_cmd, conf.co.newStateOnFlush(), io.mem_req.bits)
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}
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when ((state === s_invalid) && io.req_pri_val) {
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when (io.req_pri_val && io.req_pri_rdy) {
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line_state := conf.co.newStateOnFlush()
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refill_count := UFix(0)
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acq_type := conf.co.getAcquireTypeOnPrimaryMiss(req_cmd, conf.co.newStateOnFlush())
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req := io.req_bits
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writeback_probed := false
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state := Mux(conf.co.needsWriteback(io.req_bits.old_meta.state), s_wb_req, s_refill_req)
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when (io.req_bits.tag_match) {
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@ -264,11 +266,19 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component {
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}
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}
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val finish_q = (new Queue(2 /* wb + refill */)) { new GrantAck }
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finish_q.io.enq.valid := wb_done || refill_done
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finish_q.io.enq.bits.master_xact_id := io.mem_rep.bits.master_xact_id
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val can_finish = state === s_invalid || state === s_refill_req || state === s_refill_resp
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io.mem_finish.valid := finish_q.io.deq.valid && can_finish
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finish_q.io.deq.ready := io.mem_finish.ready && can_finish
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io.mem_finish.bits := finish_q.io.deq.bits
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io.idx_match := (state != s_invalid) && idx_match
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io.mem_resp := req
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io.mem_resp.addr := Cat(req_idx, refill_count) << conf.ramoffbits
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io.tag := req.addr >> conf.untagbits
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io.req_pri_rdy := (state === s_invalid)
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io.req_pri_rdy := state === s_invalid && !finish_q.io.deq.valid
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io.req_sec_rdy := sec_rdy && rpq.io.enq.ready
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io.meta_write.valid := state === s_meta_write_req || state === s_meta_clear
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@ -282,14 +292,12 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component {
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io.wb_req.bits.way_en := req.way_en
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io.wb_req.bits.client_xact_id := Bits(id)
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io.probe_writeback.ready := (state != s_wb_resp && state != s_meta_clear && state != s_drain_rpq) || !idx_match
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io.probe_refill.ready := (state != s_refill_resp && state != s_drain_rpq) || !idx_match
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io.mem_req.valid := state === s_refill_req
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io.mem_req.bits.a_type := acq_type
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io.mem_req.bits.addr := Cat(io.tag, req_idx).toUFix
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io.mem_req.bits.client_xact_id := Bits(id)
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io.mem_finish <> finish_q.io.deq
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io.mem_req.bits.client_xact_id := Bits(id)
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io.meta_read.valid := state === s_drain_rpq
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io.meta_read.bits.addr := io.mem_req.bits.addr << conf.offbits
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@ -351,7 +359,6 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component {
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var fence = Bool(false)
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var sec_rdy = Bool(false)
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var writeback_probe_rdy = Bool(true)
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var refill_probe_rdy = Bool(true)
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for (i <- 0 to conf.nmshr-1) {
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val mshr = new MSHR(i)
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@ -373,7 +380,6 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component {
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mshr.io.mem_finish <> mem_finish_arb.io.in(i)
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mshr.io.wb_req <> wb_req_arb.io.in(i)
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mshr.io.replay <> replay_arb.io.in(i)
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mshr.io.probe_refill.valid := io.probe.valid && tag_match
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mshr.io.probe_writeback.valid := io.probe.valid
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mshr.io.probe_writeback.bits := wb_probe_match
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@ -385,7 +391,6 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component {
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sec_rdy = sec_rdy || mshr.io.req_sec_rdy
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fence = fence || !mshr.io.req_pri_rdy
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idx_match = idx_match || mshr.io.idx_match
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refill_probe_rdy = refill_probe_rdy && mshr.io.probe_refill.ready
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writeback_probe_rdy = writeback_probe_rdy && mshr.io.probe_writeback.ready
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}
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@ -401,7 +406,7 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component {
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io.secondary_miss := idx_match
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io.mem_resp := memRespMux(io.mem_rep.bits.client_xact_id)
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io.fence_rdy := !fence
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io.probe.ready := (refill_probe_rdy || !tag_match) && (writeback_probe_rdy || !wb_probe_match)
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io.probe.ready := writeback_probe_rdy || !wb_probe_match
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val free_sdq = io.replay.fire() && isWrite(io.replay.bits.cmd)
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io.replay.bits.data := sdq(RegEn(replay_arb.io.out.bits.sdq_id, free_sdq))
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@ -1018,9 +1023,7 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio
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val acquire_arb = (new Arbiter(2)) { new Acquire }
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acquire_arb.io.in(0) <> wb.io.mem_req
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acquire_arb.io.in(1).valid := mshr.io.mem_req.valid && prober.io.req.ready
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mshr.io.mem_req.ready := acquire_arb.io.in(1).ready && prober.io.req.ready
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acquire_arb.io.in(1).bits := mshr.io.mem_req.bits
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acquire_arb.io.in(1) <> mshr.io.mem_req
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io.mem.acquire <> FIFOedLogicalNetworkIOWrapper(acquire_arb.io.out)
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io.mem.acquire_data <> FIFOedLogicalNetworkIOWrapper(wb.io.mem_req_data)
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