Prep in HellaCache for extracting MetaData to uncore
This commit is contained in:
Henry Cook
parent
5c62cff2ce
commit
f4d326b8d7
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@ -45,6 +45,7 @@ case class DCacheConfig(val sets: Int, val ways: Int,
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require(isPow2(ways)) // TODO: relax this
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require(rowbits <= tl.dataBits)
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require(lineaddrbits == tl.addrBits)
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require(untagbits <= pgidxbits)
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}
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abstract trait DCacheBundle extends Bundle {
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@ -135,15 +136,18 @@ class MetaData(implicit val conf: DCacheConfig) extends DCacheBundle {
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}
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class MetaReadReq(implicit val conf: DCacheConfig) extends DCacheBundle {
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val addr = UInt(width = conf.paddrbits)
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val idx = Bits(width = conf.idxbits)
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}
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class MetaWriteReq(implicit val conf: DCacheConfig) extends DCacheBundle {
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class MetaWriteReq(implicit conf: DCacheConfig) extends MetaReadReq()(conf) {
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val way_en = Bits(width = conf.ways)
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val idx = Bits(width = conf.idxbits)
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val data = new MetaData()
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}
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class L1MetaReadReq(implicit conf: DCacheConfig) extends MetaReadReq()(conf) {
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val tag = Bits(width = conf.tagbits)
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}
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class MSHR(id: Int)(implicit conf: DCacheConfig) extends Module {
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implicit val (tl, ln) = (conf.tl, conf.tl.ln)
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val io = new Bundle {
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@ -159,7 +163,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Module {
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val mem_req = Decoupled(new Acquire)
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val mem_resp = new DataWriteReq().asOutput
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val meta_read = Decoupled(new MetaReadReq)
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val meta_read = Decoupled(new L1MetaReadReq)
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val meta_write = Decoupled(new MetaWriteReq)
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val replay = Decoupled(new Replay)
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val mem_grant = Valid(new LogicalNetworkIO(new Grant)).flip
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@ -287,7 +291,8 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Module {
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io.mem_finish <> ackq.io.deq
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io.meta_read.valid := state === s_drain_rpq
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io.meta_read.bits.addr := io.mem_req.bits.addr << conf.offbits
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io.meta_read.bits.idx := req_idx
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io.meta_read.bits.tag := io.tag
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io.replay.valid := state === s_drain_rpq && rpq.io.deq.valid
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io.replay.bits := rpq.io.deq.bits
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@ -308,7 +313,7 @@ class MSHRFile(implicit conf: DCacheConfig) extends Module {
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val mem_req = Decoupled(new Acquire)
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val mem_resp = new DataWriteReq().asOutput
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val meta_read = Decoupled(new MetaReadReq)
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val meta_read = Decoupled(new L1MetaReadReq)
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val meta_write = Decoupled(new MetaWriteReq)
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val replay = Decoupled(new Replay)
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val mem_grant = Valid(new LogicalNetworkIO(new Grant)).flip
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@ -332,7 +337,7 @@ class MSHRFile(implicit conf: DCacheConfig) extends Module {
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val wbTagList = Vec.fill(conf.nmshr){Bits()}
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val memRespMux = Vec.fill(conf.nmshr){new DataWriteReq}
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val meta_read_arb = Module(new Arbiter(new MetaReadReq, conf.nmshr))
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val meta_read_arb = Module(new Arbiter(new L1MetaReadReq, conf.nmshr))
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val meta_write_arb = Module(new Arbiter(new MetaWriteReq, conf.nmshr))
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val mem_req_arb = Module(new Arbiter(new Acquire, conf.nmshr))
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val mem_finish_arb = Module(new Arbiter(new LogicalNetworkIO(new GrantAck), conf.nmshr))
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@ -406,7 +411,7 @@ class WritebackUnit(implicit conf: DCacheConfig) extends Module {
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implicit val tl = conf.tl
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val io = new Bundle {
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val req = Decoupled(new WritebackReq()).flip
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val meta_read = Decoupled(new MetaReadReq)
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val meta_read = Decoupled(new L1MetaReadReq)
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val data_req = Decoupled(new DataReadReq())
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val data_resp = Bits(INPUT, conf.encrowbits)
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val release = Decoupled(new Release)
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@ -455,7 +460,8 @@ class WritebackUnit(implicit conf: DCacheConfig) extends Module {
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// We reissue the meta read as it sets up the muxing for s2_data_muxed
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io.meta_read.valid := fire
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io.meta_read.bits.addr := io.release.bits.addr << conf.offbits
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io.meta_read.bits.idx := req.idx
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io.meta_read.bits.tag := req.tag
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io.data_req.valid := fire
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io.data_req.bits.way_en := req.way_en
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@ -486,7 +492,7 @@ class ProbeUnit(implicit conf: DCacheConfig) extends Module {
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val io = new Bundle {
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val req = Decoupled(new InternalProbe).flip
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val rep = Decoupled(new Release)
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val meta_read = Decoupled(new MetaReadReq)
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val meta_read = Decoupled(new L1MetaReadReq)
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val meta_write = Decoupled(new MetaWriteReq)
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val wb_req = Decoupled(new WritebackReq)
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val way_en = Bits(INPUT, conf.ways)
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@ -541,7 +547,8 @@ class ProbeUnit(implicit conf: DCacheConfig) extends Module {
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io.rep.bits := Release(tl.co.getReleaseTypeOnProbe(req, Mux(hit, line_state, tl.co.newStateOnFlush)), req.addr, req.client_xact_id, req.master_xact_id)
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io.meta_read.valid := state === s_meta_read
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io.meta_read.bits.addr := req.addr << conf.offbits
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io.meta_read.bits.idx := req.addr
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io.meta_read.bits.tag := req.addr >> conf.idxbits
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io.meta_write.valid := state === s_meta_write
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io.meta_write.bits.way_en := way_en
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@ -579,7 +586,7 @@ class MetaDataArray(implicit conf: DCacheConfig) extends Module {
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val mask = Mux(rst, SInt(-1), io.write.bits.way_en)
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tags.write(addr, Fill(conf.ways, data), FillInterleaved(metabits, mask))
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}
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val tag = tags(RegEnable(io.read.bits.addr >> conf.offbits, io.read.valid))
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val tag = tags(RegEnable(io.read.bits.idx, io.read.valid))
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for (w <- 0 until conf.ways) {
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val m = tag(metabits*(w+1)-1, metabits*w)
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@ -775,11 +782,11 @@ class HellaCache(implicit conf: DCacheConfig) extends Module {
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s1_req := io.cpu.req.bits
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}
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when (wb.io.meta_read.valid) {
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s1_req := wb.io.meta_read.bits
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s1_req.addr := Cat(wb.io.meta_read.bits.tag, wb.io.meta_read.bits.idx) << conf.offbits
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s1_req.phys := Bool(true)
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}
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when (prober.io.meta_read.valid) {
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s1_req := prober.io.meta_read.bits
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s1_req.addr := Cat(prober.io.meta_read.bits.tag, prober.io.meta_read.bits.idx) << conf.offbits
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s1_req.phys := Bool(true)
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}
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when (mshrs.io.replay.valid) {
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@ -833,7 +840,7 @@ class HellaCache(implicit conf: DCacheConfig) extends Module {
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// tag read for new requests
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metaReadArb.io.in(4).valid := io.cpu.req.valid
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metaReadArb.io.in(4).bits.addr := io.cpu.req.bits.addr
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metaReadArb.io.in(4).bits.idx := io.cpu.req.bits.addr >> conf.offbits
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when (!metaReadArb.io.in(4).ready) { io.cpu.req.ready := Bool(false) }
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// data read for new requests
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@ -844,7 +851,7 @@ class HellaCache(implicit conf: DCacheConfig) extends Module {
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// recycled requests
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metaReadArb.io.in(0).valid := s2_recycle
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metaReadArb.io.in(0).bits.addr := s2_req.addr
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metaReadArb.io.in(0).bits.idx := s2_req.addr >> conf.offbits
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readArb.io.in(0).valid := s2_recycle
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readArb.io.in(0).bits.addr := s2_req.addr
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readArb.io.in(0).bits.way_en := SInt(-1)
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