fix dcache tag array size
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@ -605,7 +605,7 @@ class MetaDataArrayArray(lines: Int) extends Component {
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val permBits = io.req.bits.data.state.width
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val perms = Mem(lines) { UFix(width = permBits*NWAYS) }
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val tags = Mem(lines*NWAYS, seqRead = true) { Bits(width = TAG_BITS*NWAYS) }
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val tags = Mem(lines, seqRead = true) { Bits(width = TAG_BITS*NWAYS) }
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val tag = Reg() { Bits() }
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val raddr = Reg() { Bits() }
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val way_en_ = Reg { Bits(width=NWAYS) }
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