fix metadata default, add bug TODO
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@ -771,7 +771,7 @@ class HellaCache(implicit conf: DCacheConfig) extends Module {
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io.cpu.xcpt.pf.st := s1_write && dtlb.io.resp.xcpt_st
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// tags
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def onReset = L1MetaData(tl.co.newStateOnFlush, UInt(0))
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def onReset = L1MetaData(UInt(0), tl.co.newStateOnFlush)
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val meta = Module(new MetaDataArray(onReset _))
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val metaReadArb = Module(new Arbiter(new MetaReadReq, 5))
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val metaWriteArb = Module(new Arbiter(new MetaWriteReq(new L1MetaData), 2))
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@ -810,7 +810,7 @@ class HellaCache(implicit conf: DCacheConfig) extends Module {
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def wayMap[T <: Data](f: Int => T) = Vec((0 until conf.ways).map(f))
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val s1_tag_eq_way = wayMap((w: Int) => meta.io.resp(w).tag === (s1_addr >> conf.untagbits)).toBits
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val s1_tag_match_way = wayMap((w: Int) => s1_tag_eq_way(w) && tl.co.isValid(meta.io.resp(w).state)).toBits
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s1_clk_en := metaReadArb.io.out.valid
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s1_clk_en := metaReadArb.io.out.valid //TODO: should be metaReadArb.io.out.fire(), but triggers Verilog backend bug
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val s1_writeback = s1_clk_en && !s1_valid && !s1_replay
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val s2_tag_match_way = RegEnable(s1_tag_match_way, s1_clk_en)
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val s2_tag_match = s2_tag_match_way.orR
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