don't use reset combinationally
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@ -508,7 +508,7 @@ class ProbeUnit(implicit conf: DCacheConfig) extends Component {
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val line_state = UFix(INPUT, 2)
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}
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val s_invalid :: s_meta_read :: s_meta_resp :: s_mshr_req :: s_release :: s_writeback_req :: s_writeback_resp :: s_meta_write :: Nil = Enum(8) { UFix() }
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val s_reset :: s_invalid :: s_meta_read :: s_meta_resp :: s_mshr_req :: s_release :: s_writeback_req :: s_writeback_resp :: s_meta_write :: Nil = Enum(9) { UFix() }
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val state = Reg(resetVal = s_invalid)
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val line_state = Reg() { UFix() }
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val way_en = Reg() { Bits() }
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@ -546,8 +546,11 @@ class ProbeUnit(implicit conf: DCacheConfig) extends Component {
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state := s_meta_read
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req := io.req.bits
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}
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when (state === s_reset) {
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state := s_invalid
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}
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io.req.ready := state === s_invalid && !reset
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io.req.ready := state === s_invalid
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io.rep.valid := state === s_release
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io.rep.bits := conf.co.newRelease(req, Mux(hit, line_state, conf.co.newStateOnFlush))
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