Refactored uncore conf
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78868f6075
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261e14f831
@ -36,11 +36,11 @@ class ioHTIF(ntiles: Int) extends Bundle
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val ipi_rep = (new FIFOIO) { Bool() }.flip
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}
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class rocketHTIF(w: Int)(implicit conf: UncoreConfiguration) extends Component
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class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Component with ClientCoherenceAgent
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{
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val io = new Bundle {
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val host = new ioHost(w)
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val cpu = Vec(conf.ntiles) { new ioHTIF(conf.ntiles).flip }
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val cpu = Vec(conf.ln.nTiles) { new ioHTIF(conf.ln.nTiles).flip }
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val mem = new ioTileLink
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}
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@ -81,7 +81,7 @@ class rocketHTIF(w: Int)(implicit conf: UncoreConfiguration) extends Component
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val cmd_readmem :: cmd_writemem :: cmd_readcr :: cmd_writecr :: cmd_ack :: cmd_nack :: Nil = Enum(6) { UFix() }
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val pcr_addr = addr(io.cpu(0).pcr_req.bits.addr.width-1, 0)
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val pcr_coreid = if (conf.ntiles == 1) UFix(0) else addr(20+log2Up(conf.ntiles),20)
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val pcr_coreid = if (conf.ln.nTiles == 1) UFix(0) else addr(20+log2Up(conf.ln.nTiles),20)
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val pcr_wdata = packet_ram(0)
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val bad_mem_packet = size(OFFSET_BITS-1-3,0).orR || addr(OFFSET_BITS-1-3,0).orR
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@ -193,8 +193,8 @@ class rocketHTIF(w: Int)(implicit conf: UncoreConfiguration) extends Component
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io.mem.probe_rep_data.valid := Bool(false)
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io.mem.incoherent := Bool(true)
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val pcrReadData = Vec(conf.ntiles) { Reg() { Bits(width = io.cpu(0).pcr_rep.bits.getWidth) } }
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for (i <- 0 until conf.ntiles) {
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val pcrReadData = Vec(conf.ln.nTiles) { Reg() { Bits(width = io.cpu(0).pcr_rep.bits.getWidth) } }
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for (i <- 0 until conf.ln.nTiles) {
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val my_reset = Reg(resetVal = Bool(true))
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val my_ipi = Reg(resetVal = Bool(false))
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@ -211,7 +211,7 @@ class rocketHTIF(w: Int)(implicit conf: UncoreConfiguration) extends Component
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}
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cpu.ipi_rep.valid := my_ipi
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cpu.ipi_req.ready := Bool(true)
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for (j <- 0 until conf.ntiles) {
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for (j <- 0 until conf.ln.nTiles) {
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when (io.cpu(j).ipi_req.valid && io.cpu(j).ipi_req.bits === UFix(i)) {
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my_ipi := Bool(true)
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}
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@ -858,7 +858,7 @@ class HellaCache(implicit conf: DCacheConfig) extends Component {
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readArb.io.in(0).bits.way_en := Fix(-1)
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// tag check and way muxing
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def wayMap[T <: Data](f: Int => T)(gen: => T) = Vec((0 until conf.ways).map(i => f(i))){gen}
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def wayMap[T <: Data](f: Int => T)(gen: => T) = Vec((0 until conf.ways).map(f)){gen}
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val s1_tag_eq_way = wayMap((w: Int) => meta.io.resp(w).tag === (s1_addr >> conf.untagbits)){Bits()}.toBits
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val s1_tag_match_way = wayMap((w: Int) => s1_tag_eq_way(w) && conf.co.isValid(meta.io.resp(w).state)){Bits()}.toBits
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s1_clk_en := metaReadArb.io.out.valid
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@ -21,7 +21,7 @@ case class RocketConfiguration(ntiles: Int, co: CoherencePolicyWithUncached,
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if (fastLoadByte) require(fastLoadWord)
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}
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class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Component(resetSignal)
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class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Component(resetSignal) with ClientCoherenceAgent
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{
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val memPorts = 2 + confIn.vec
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implicit val dcConf = confIn.dcache.copy(reqtagbits = confIn.dcacheReqTagBits + log2Up(memPorts), databits = confIn.xprlen)
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