Wesley W. Terpstra
9c38f20333
vc707 axi: move addresses to line up with ChipLink
2018-02-08 07:21:44 -08:00
Henry Styles
61ece0bf00
VC707 Shell : additional skewed clocks
2018-02-08 07:21:44 -08:00
Henry Styles
0fdbb778bf
VC707 Shell : move DebugJTAG pins and connect function into a separate mix-in
2018-02-08 07:21:44 -08:00
Henry Styles
045b290fbd
VC707 JTAG support throught XM105 FMC or reuse of LCD header
2018-02-08 07:21:44 -08:00
Henry Styles
f9dc552ddc
Xilinx unisim typo
2018-02-08 07:21:44 -08:00
Henry Styles
33c88b8cc4
Move Xilinx unisims into separate file
2018-02-08 07:21:44 -08:00
Wesley W. Terpstra
8b0d7ec91a
TransferSizes: just because a device CAN do more does not mean it should ( #15 )
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Capping TransferSizes at 128 fits nicely in 3 size bits.
2017-12-10 00:42:11 -08:00
Henry Styles
ba7beb676d
Merge pull request #14 from sifive/vc707_mig_pcie_traits
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VC707 Shell : Make DDR and PCIe optional, mixed into Shell with traits
2017-11-01 16:58:44 -07:00
Henry Styles
e1bfb75188
VC707 Shell : Make DDR and PCIe optional, mixed into Shell with traits. Also add MMCM to provide 65Mhz (and multiples) clock
2017-11-01 14:23:07 -07:00
Wesley W. Terpstra
df8e6b8e8c
xilinxvc707pciex1: use new node-style API and abstract crossing ( #13 )
2017-10-28 12:27:24 -07:00
Wesley W. Terpstra
65ac5d4588
xilinxVC707mig: convert to the island pattern ( #12 )
2017-10-26 16:38:52 -07:00
Henry Styles
eaf1c3ed54
Merge pull request #11 from sifive/vc707_use_ip_io_bundles
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VC707 use IP IO bundles
2017-10-24 17:49:31 -07:00
Henry Styles
dc6bb40d1b
VC707 : update contraints file to match PCIe and MIG signal names now claimed directly from the IP
2017-10-23 17:27:36 -07:00
Henry Styles
61b167e8d9
VC707 : use IO bundles directly from the PCIe and MIG devices instead of redeclaring signals
2017-10-23 16:53:59 -07:00
Wesley W. Terpstra
d8e50c7646
TLToAXI4: remove now unnecessary argument ( #10 )
2017-10-12 14:37:21 -07:00
Richard Xia
66e5ac2e9e
Merge pull request #8 from sifive/replace-env-vars-with-cli-args
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Restructure Tcl script entrypoint.
2017-10-04 14:28:10 -07:00
Richard Xia
9593e5eee6
Restructure Tcl script entrypoint.
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vivado.tcl is now the entrypoint for the Vivado Tcl scripts and will
automatically source all the other required scripts.
A command line argument parser was written and replaces the previous system of
using environment variables to pass values into the scripts. The VSRCSVIVADOTCL
environment variable has been replaced with a -F command line option, and the
file format has changed from a Tcl script to a simple newline-delimited list of
files.
2017-10-04 14:15:39 -07:00
Wesley W. Terpstra
4af0552374
diplomacy: update to new API ( #7 )
2017-09-27 16:32:43 -07:00
Megan Wachs
32d4083890
Merge pull request #6 from sifive/signal_bundles
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signal_bundles: Use the new way as .fromPorts is gone
2017-09-25 11:20:44 -07:00
Megan Wachs
bf48e2c7c4
signal_bundles: Use the new way as .fromPorts is gone
2017-09-22 13:31:11 -07:00
Henry Styles
e9019d7570
Merge pull request #5 from sifive/vivado_vsrcs_using_file
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Use a file instead of environment variable to pass VSRCS into Vivado
2017-09-19 14:13:36 -07:00
Henry Styles
97e628639a
Use a file instead of environment variable to pass VSRCS into Vivado
2017-09-19 14:12:23 -07:00
Henry Styles
2bed0c30dc
correct invoke of board specific ip.tcl
2017-09-08 23:20:55 -07:00
Henry Styles
07b2ae07d2
Merge pull request #4 from sifive/vc707_2GB
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Support both 4G and 1GB DIMM configuration for VC707
2017-09-08 16:09:18 -07:00
Henry Styles
9f75e6eb59
Support both 4G and 1GB DIMM configuration for VC707
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Generate IP TCL and MIG projects from the Chisel blackboxes
2017-09-08 15:52:53 -07:00
Megan Wachs
e49f49686d
Merge pull request #1 from sifive/synchronizers
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synchronizers: Use new primitives
2017-09-07 13:33:26 -07:00
Megan Wachs
31650a2d23
Merge remote-tracking branch 'origin/master' into synchronizers
2017-09-07 10:46:03 -07:00
Henry Styles
385ffa7d9a
Merge pull request #3 from sifive/freedomu500vc707devkit_fix_xdc
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fix PCIe vc707 design contraints : PCIe pins and UART RX sync register
2017-09-07 10:42:32 -07:00
Henry Styles
b7ee0ab0f0
fix PCIe vc707 design contraints : PCIe pins and UART RX sync register
2017-09-07 10:41:12 -07:00
Megan Wachs
cab572fab2
synchronizers: decided that ShiftRegInit should be reversed as the others.
2017-09-07 09:54:35 -07:00
Megan Wachs
fd70d118d3
synchronizers: Update constraints to match new hierarchy for synchronizers
2017-09-07 07:50:22 -07:00
Megan Wachs
13671f906d
synchronizers: Use new primitives
2017-09-06 11:00:25 -07:00
Shreesha Srinath
2389e6e957
Fix the package path for xilinx vc707mig
2017-08-18 14:47:03 -07:00
Shreesha Srinath
38afe2957f
Fixing typos in the tcl script
2017-08-18 11:34:35 -07:00
Shreesha Srinath
ae767458af
Pass debug hooks through project-specific makefiles
2017-08-18 11:27:02 -07:00
Shreesha Srinath
c58e79f155
vc707: Updates to the constraints and shell
2017-08-17 18:51:01 -07:00
Shreesha Srinath
ab8cf0775f
Initial commit for fpga-shells
2017-08-16 11:23:45 -07:00
