Shreesha Srinath 38afe2957f Fixing typos in the tcl script

2017-08-18 11:34:35 -07:00

src/main/scala

vc707: Updates to the constraints and shell

2017-08-17 18:51:01 -07:00

xilinx

Fixing typos in the tcl script

2017-08-18 11:34:35 -07:00

.gitignore

Initial commit for fpga-shells

2017-08-16 11:23:45 -07:00

build.sbt

Initial commit for fpga-shells

2017-08-16 11:23:45 -07:00

S

Description

Freedom FPGA mappings (https://github.com/sifive/fpga-shells)

682 KiB

Languages

Scala 89.5%

Tcl 7.8%

Verilog 2%

Makefile 0.7%