This website requires JavaScript.
Explore
Help
Sign In
riscv
/
sifive-blocks
Watch
1
Star
0
Fork
0
You've already forked sifive-blocks
Code
Releases
Activity
132
Commits
1
Branch
0
Tags
3dee15277598e45d7ac9d435f0365989c6d00f7e
Go to file
Code
Clone
HTTPS
Tea CLI
Open with VS Code
Open with VSCodium
Open with Intellij IDEA
Download ZIP
Download TAR.GZ
Download BUNDLE
solomatnikov
3dee152775
Bug fix: arbLost should be asserted when bitState =/= s_bit_idle (
#49
)
2018-02-23 12:09:18 -08:00
src/main
/scala
Bug fix: arbLost should be asserted when bitState =/= s_bit_idle (
#49
)
2018-02-23 12:09:18 -08:00
vsrc
Updates to go with the fpga-shells directory
2017-08-17 18:12:49 -07:00
.gitignore
Add /target to .gitignore.
2016-11-30 13:29:54 -08:00
LICENSE
Initial commit.
2016-11-29 04:08:44 -08:00
Description
Freedom RTL blocks (
https://github.com/sifive/sifive-blocks
)
280
KiB
Languages
Scala
99.8%
Verilog
0.2%
