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Merge pull request #52 from sifive/spi_sync

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SPI: Use the standard synchronizer primitive for the SPI DQ inputs
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Megan Wachs 2018-03-07 14:45:44 -08:00 committed by GitHub
commit 48a9acc8a4
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1 changed files with 3 additions and 2 deletions
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5
src/main/scala/devices/spi/SPIPins.scala
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@ -3,6 +3,7 @@ package sifive.blocks.devices.spi
import Chisel._
import chisel3.experimental.{withClockAndReset}
import freechips.rocketchip.util.{SynchronizerShiftReg}
import sifive.blocks.devices.pinctrl.{PinCtrl, Pin}
class SPISignals[T <: Data](private val pingen: () => T, c: SPIParamsBase) extends SPIBundle(c) {
@ -22,11 +23,11 @@ object SPIPinsFromPort {
withClockAndReset(clock, reset) {
pins.sck.outputPin(spi.sck, ds = driveStrength)
(pins.dq zip spi.dq).foreach {case (p, s) =>
(pins.dq zip spi.dq).zipWithIndex.foreach {case ((p, s), i) =>
p.outputPin(s.o, pue = Bool(true), ds = driveStrength)
p.o.oe := s.oe
p.o.ie := ~s.oe
s.i := ShiftRegister(p.i.ival, syncStages)
s.i := SynchronizerShiftReg(p.i.ival, syncStages, name = Some(s"spi_dq_${i}_sync"))
}
(pins.cs zip spi.cs) foreach { case (c, s) =>