This website requires JavaScript.
Explore
Help
Sign In
riscv
/
sifive-blocks
Watch
1
Star
0
Fork
0
You've already forked sifive-blocks
Code
Releases
Activity
125
Commits
1
Branch
0
Tags
d1d2f47f609638c43546d4a9d0a4018c73dee4bb
Go to file
Code
Clone
HTTPS
Tea CLI
Open with VS Code
Open with VSCodium
Open with Intellij IDEA
Download ZIP
Download TAR.GZ
Download BUNDLE
Wesley W. Terpstra
d1d2f47f60
PMU: adapt to new chisel API (
#45
)
2017-11-02 15:44:02 -07:00
src/main
/scala
PMU: adapt to new chisel API (
#45
)
2017-11-02 15:44:02 -07:00
vsrc
Updates to go with the fpga-shells directory
2017-08-17 18:12:49 -07:00
.gitignore
Add /target to .gitignore.
2016-11-30 13:29:54 -08:00
LICENSE
Initial commit.
2016-11-29 04:08:44 -08:00
Description
Freedom RTL blocks (
https://github.com/sifive/sifive-blocks
)
280
KiB
Languages
Scala
99.8%
Verilog
0.2%