riscv/sifive-blocks
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Shreesha Srinath 249c23e617 Renamed ShiftReg to ShiftRegister
2017-08-17 18:22:51 -07:00
src/main/scala
Renamed ShiftReg to ShiftRegister
2017-08-17 18:22:51 -07:00
vsrc
Updates to go with the fpga-shells directory
2017-08-17 18:12:49 -07:00
.gitignore
Add /target to .gitignore.
2016-11-30 13:29:54 -08:00
LICENSE
Initial commit.
2016-11-29 04:08:44 -08:00
Description
Freedom RTL blocks (https://github.com/sifive/sifive-blocks)
280 KiB
Languages
Scala 99.8%
Verilog 0.2%