Megan Wachs fe65a87c5c Merge pull request #39 from sifive/signal_bundles ...

Create Signal Bundles vs just Pins

2017-09-25 11:21:08 -07:00

src/main/scala

GPIO Pins needs clone type.

2017-09-22 16:38:37 -07:00

vsrc

Updates to go with the fpga-shells directory

2017-08-17 18:12:49 -07:00

.gitignore

Add /target to .gitignore.

2016-11-30 13:29:54 -08:00

LICENSE

Initial commit.

2016-11-29 04:08:44 -08:00

S

Description

Freedom RTL blocks (https://github.com/sifive/sifive-blocks)

280 KiB

Languages

Scala 99.8%

Verilog 0.2%