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periphery: bus api update (#50)

This commit is contained in:
Henry Cook 2018-03-01 01:15:02 -08:00 committed by GitHub
parent 3dee152775
commit 00fbfb6dd8
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GPG Key ID: 4AEE18F83AFDEB23
8 changed files with 44 additions and 49 deletions
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11
src/main/scala/devices/gpio/GPIOPeriphery.scala
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@ -3,17 +3,18 @@ package sifive.blocks.devices.gpio
import Chisel._
import freechips.rocketchip.config.Field
import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
import freechips.rocketchip.subsystem.BaseSubsystem
import freechips.rocketchip.diplomacy.{LazyModule,LazyModuleImp}
import freechips.rocketchip.util.HeterogeneousBag
case object PeripheryGPIOKey extends Field[Seq[GPIOParams]]
trait HasPeripheryGPIO extends HasPeripheryBus with HasInterruptBus {
trait HasPeripheryGPIO { this: BaseSubsystem =>
val gpioParams = p(PeripheryGPIOKey)
val gpios = gpioParams map { params =>
val gpio = LazyModule(new TLGPIO(pbus.beatBytes, params))
gpio.node := pbus.toVariableWidthSlaves
val gpios = gpioParams.zipWithIndex.map { case(params, i) =>
val name = Some(s"gpio_$i")
val gpio = LazyModule(new TLGPIO(pbus.beatBytes, params)).suggestName(name)
pbus.toVariableWidthSlave(name) { gpio.node }
ibus.fromSync := gpio.intnode
gpio
}

11
src/main/scala/devices/i2c/I2CPeriphery.scala
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@ -3,16 +3,17 @@ package sifive.blocks.devices.i2c
import Chisel._
import freechips.rocketchip.config.Field
import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
import freechips.rocketchip.subsystem.BaseSubsystem
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
case object PeripheryI2CKey extends Field[Seq[I2CParams]]
trait HasPeripheryI2C extends HasPeripheryBus {
trait HasPeripheryI2C { this: BaseSubsystem =>
val i2cParams = p(PeripheryI2CKey)
val i2c = i2cParams map { params =>
val i2c = LazyModule(new TLI2C(pbus.beatBytes, params))
i2c.node := pbus.toVariableWidthSlaves
val i2c = i2cParams.zipWithIndex.map { case(params, i) =>
val name = Some(s"i2c_$i")
val i2c = LazyModule(new TLI2C(pbus.beatBytes, params)).suggestName(name)
pbus.toVariableWidthSlave(name) { i2c.node }
ibus.fromSync := i2c.intnode
i2c
}

16
src/main/scala/devices/mockaon/MockAONPeriphery.scala
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@ -3,26 +3,22 @@ package sifive.blocks.devices.mockaon
import Chisel._
import freechips.rocketchip.config.Field
import freechips.rocketchip.util.SynchronizerShiftReg
import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
import freechips.rocketchip.devices.debug.HasPeripheryDebug
import freechips.rocketchip.devices.tilelink.HasPeripheryClint
import freechips.rocketchip.devices.tilelink.HasPeripheryCLINT
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
import freechips.rocketchip.tilelink.{TLAsyncCrossingSource}
import freechips.rocketchip.interrupts._
import freechips.rocketchip.util.ResetCatchAndSync
import freechips.rocketchip.subsystem.BaseSubsystem
import freechips.rocketchip.tilelink.{TLAsyncCrossingSource}
import freechips.rocketchip.util.{ResetCatchAndSync, SynchronizerShiftReg}
case object PeripheryMockAONKey extends Field[MockAONParams]
trait HasPeripheryMockAON extends HasPeripheryBus
with HasInterruptBus
with HasPeripheryClint
with HasPeripheryDebug {
trait HasPeripheryMockAON extends HasPeripheryCLINT with HasPeripheryDebug { this: BaseSubsystem =>
// We override the clock & Reset here so that all synchronizers, etc
// are in the proper clock domain.
val mockAONParams= p(PeripheryMockAONKey)
val aon = LazyModule(new MockAONWrapper(pbus.beatBytes, mockAONParams))
aon.node := TLAsyncCrossingSource() := pbus.toVariableWidthSlaves
pbus.toVariableWidthSlave(Some("aon")) { aon.node := TLAsyncCrossingSource() }
ibus.fromSync := IntSyncCrossingSink() := aon.intnode
}

11
src/main/scala/devices/pwm/PWMPeriphery.scala
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@ -3,7 +3,7 @@ package sifive.blocks.devices.pwm
import Chisel._
import freechips.rocketchip.config.Field
import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
import freechips.rocketchip.subsystem.BaseSubsystem
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
import freechips.rocketchip.util.HeterogeneousBag
import sifive.blocks.devices.pinctrl.{Pin}
@ -16,11 +16,12 @@ class PWMPortIO(val c: PWMParams) extends Bundle {
case object PeripheryPWMKey extends Field[Seq[PWMParams]]
trait HasPeripheryPWM extends HasPeripheryBus with HasInterruptBus {
trait HasPeripheryPWM { this: BaseSubsystem =>
val pwmParams = p(PeripheryPWMKey)
val pwms = pwmParams map { params =>
val pwm = LazyModule(new TLPWM(pbus.beatBytes, params))
pwm.node := pbus.toVariableWidthSlaves
val pwms = pwmParams.zipWithIndex.map { case(params, i) =>
val name = Some(s"pwm_$i")
val pwm = LazyModule(new TLPWM(pbus.beatBytes, params)).suggestName(name)
pbus.toVariableWidthSlave(name) { pwm.node }
ibus.fromSync := pwm.intnode
pwm
}

4
src/main/scala/devices/pwm/PWMPins.scala
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@ -2,10 +2,6 @@
package sifive.blocks.devices.pwm
import Chisel._
import freechips.rocketchip.config.Field
import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
import freechips.rocketchip.util.HeterogeneousBag
import sifive.blocks.devices.pinctrl.{Pin}
class PWMSignals[T <: Data] (pingen: ()=> T, val c: PWMParams) extends Bundle {

26
src/main/scala/devices/spi/SPIPeriphery.scala
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@ -3,18 +3,19 @@ package sifive.blocks.devices.spi
import Chisel._
import freechips.rocketchip.config.Field
import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
import freechips.rocketchip.subsystem.BaseSubsystem
import freechips.rocketchip.diplomacy.{LazyModule,LazyModuleImp,BufferParams}
import freechips.rocketchip.tilelink.{TLFragmenter,TLBuffer}
import freechips.rocketchip.util.HeterogeneousBag
case object PeripherySPIKey extends Field[Seq[SPIParams]]
trait HasPeripherySPI extends HasPeripheryBus with HasInterruptBus {
trait HasPeripherySPI { this: BaseSubsystem =>
val spiParams = p(PeripherySPIKey)
val spis = spiParams map { params =>
val spi = LazyModule(new TLSPI(pbus.beatBytes, params))
spi.rnode := pbus.toVariableWidthSlaves
val spis = spiParams.zipWithIndex.map { case(params, i) =>
val name = Some(s"spi_$i")
val spi = LazyModule(new TLSPI(pbus.beatBytes, params)).suggestName(name)
pbus.toVariableWidthSlave(name) { spi.rnode }
ibus.fromSync := spi.intnode
spi
}
@ -36,15 +37,16 @@ trait HasPeripherySPIModuleImp extends LazyModuleImp with HasPeripherySPIBundle
case object PeripherySPIFlashKey extends Field[Seq[SPIFlashParams]]
trait HasPeripherySPIFlash extends HasPeripheryBus with HasInterruptBus {
trait HasPeripherySPIFlash { this: BaseSubsystem =>
val spiFlashParams = p(PeripherySPIFlashKey)
val qspis = spiFlashParams map { params =>
val qspis = spiFlashParams.zipWithIndex.map { case(params, i) =>
val name = Some(s"qspi_$i")
val qspi = LazyModule(new TLSPIFlash(pbus.beatBytes, params))
qspi.rnode := pbus.toVariableWidthSlaves
(qspi.fnode
:= TLFragmenter(1, pbus.blockBytes)
:= TLBuffer(BufferParams(params.fBufferDepth), BufferParams.none)
:= pbus.toFixedWidthSlaves)
pbus.toVariableWidthSlave(name) { qspi.rnode }
qspi.fnode := pbus.toFixedWidthSlave(name) {
TLFragmenter(1, pbus.blockBytes) :=
TLBuffer(BufferParams(params.fBufferDepth), BufferParams.none)
}
ibus.fromSync := qspi.intnode
qspi
}

11
src/main/scala/devices/uart/UARTPeriphery.scala
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@ -4,17 +4,18 @@ package sifive.blocks.devices.uart
import Chisel._
import chisel3.experimental.{withClockAndReset}
import freechips.rocketchip.config.Field
import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusKey, HasInterruptBus}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
import freechips.rocketchip.subsystem.{BaseSubsystem, PeripheryBusKey}
case object PeripheryUARTKey extends Field[Seq[UARTParams]]
trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus {
trait HasPeripheryUART { this: BaseSubsystem =>
private val divinit = (p(PeripheryBusKey).frequency / 115200).toInt
val uartParams = p(PeripheryUARTKey).map(_.copy(divisorInit = divinit))
val uarts = uartParams map { params =>
val uart = LazyModule(new TLUART(pbus.beatBytes, params))
uart.node := pbus.toVariableWidthSlaves
val uarts = uartParams.zipWithIndex.map { case(params, i) =>
val name = Some(s"uart_$i")
val uart = LazyModule(new TLUART(pbus.beatBytes, params)).suggestName(name)
pbus.toVariableWidthSlave(name) { uart.node }
ibus.fromSync := uart.intnode
uart
}

3
src/main/scala/devices/uart/UARTPins.scala
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@ -3,10 +3,7 @@ package sifive.blocks.devices.uart
import Chisel._
import chisel3.experimental.{withClockAndReset}
import freechips.rocketchip.config.Field
import freechips.rocketchip.util.SyncResetSynchronizerShiftReg
import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusKey, HasInterruptBus}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
import sifive.blocks.devices.pinctrl.{Pin}
class UARTSignals[T <: Data] (pingen: () => T) extends Bundle {