Megan WachsandGitHub d5554bfe95 Merge pull request #37 from sifive/synchronizers ...

remove duplicate ResetCatchAndSync definition

2017-09-07 13:34:14 -07:00

src/main/scala

shiftregs: Use SyncResetSynchronizerShiftReg primitives where appropriate

2017-09-06 10:59:07 -07:00

vsrc

Updates to go with the fpga-shells directory

2017-08-17 18:12:49 -07:00

.gitignore

Add /target to .gitignore.

2016-11-30 13:29:54 -08:00

LICENSE

Initial commit.

2016-11-29 04:08:44 -08:00

S

Description

Freedom RTL blocks (https://github.com/sifive/sifive-blocks)

280 KiB

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Verilog 0.2%