Megan WachsandGitHub e6da80733e Merge pull request #42 from sifive/enhanced_to_base_pin ...

pinctrl: Add the ability to convert EnhancedPin to BasePin

2017-10-11 06:43:41 -07:00

src/main/scala

pinctrl: Add the ability to convert EnhancedPin to BasePin

2017-10-06 13:43:23 -07:00

vsrc

Updates to go with the fpga-shells directory

2017-08-17 18:12:49 -07:00

.gitignore

Add /target to .gitignore.

2016-11-30 13:29:54 -08:00

LICENSE

Initial commit.

2016-11-29 04:08:44 -08:00

S

Description

Freedom RTL blocks (https://github.com/sifive/sifive-blocks)

280 KiB

Languages

Scala 99.8%

Verilog 0.2%