Freedom RTL blocks (https://github.com/sifive/sifive-blocks)
14ffd35f5c
This refactors the receiver logic to compensate for the case of the baud rate divisor not being multiple of the oversampling period. Previously, the bit time was effectively rounded to (s * floor(div / s)) cycles, where "s" is the oversampling factor - the number of intermediate samples for each data bit. The remainder r = (div % s) was ignored, thereby resulting in gradually accumulated drift that became significant for divisor values on the same order of magnitude as "s". The revised approach inserts the required additional delay by extending the last "r" samples of a given data bit by one cycle each. |
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| src/main/scala | ||
| vsrc | ||
| .gitignore | ||
| LICENSE | ||