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riscv
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sifive-blocks
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fb4977b518d20fcb3a5011a2725425b1ad709efa
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Megan Wachs
fb4977b518
SPI: Use the standard synchronizer primitive for the SPI DQ inputs
2018-03-07 09:54:56 -08:00
src/main
/scala
SPI: Use the standard synchronizer primitive for the SPI DQ inputs
2018-03-07 09:54:56 -08:00
vsrc
Updates to go with the fpga-shells directory
2017-08-17 18:12:49 -07:00
.gitignore
Add /target to .gitignore.
2016-11-30 13:29:54 -08:00
LICENSE
Initial commit.
2016-11-29 04:08:44 -08:00
S
Description
Freedom RTL blocks (
https://github.com/sifive/sifive-blocks
)
280
KiB
Languages
Scala
99.8%
Verilog
0.2%
