Wesley W. TerpstraandGitHub 7ac56c01af Merge pull request #53 from sifive/chiplink ...

devices: add support for the chiplink protocol

2018-03-22 16:18:30 -07:00

src/main/scala

msi: add a MSIMaster to bridge interrupts over ChipLink

2018-03-22 16:06:12 -07:00

vsrc

Updates to go with the fpga-shells directory

2017-08-17 18:12:49 -07:00

.gitignore

Add /target to .gitignore.

2016-11-30 13:29:54 -08:00

LICENSE

Initial commit.

2016-11-29 04:08:44 -08:00

S

Description

Freedom RTL blocks (https://github.com/sifive/sifive-blocks)

280 KiB

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Scala 99.8%

Verilog 0.2%