Logo
Explore Help
Sign In
riscv/sifive-blocks
Watch 1
Star 0 Fork 0
Code Releases Activity
141 Commits 1 Branch 0 Tags
d7b9834d96829575a84f83b48cacba7b6b3d9cbe
T
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
klemens d7b9834d96 Add TLTerminal (write-only terminal TL slave)
2018-04-30 00:45:27 +02:00
src/main/scala
Add TLTerminal (write-only terminal TL slave)
2018-04-30 00:45:27 +02:00
vsrc
Updates to go with the fpga-shells directory
2017-08-17 18:12:49 -07:00
.gitignore
Add /target to .gitignore.
2016-11-30 13:29:54 -08:00
LICENSE
Initial commit.
2016-11-29 04:08:44 -08:00
S
Description
Freedom RTL blocks (https://github.com/sifive/sifive-blocks)
280 KiB
0 Stars 1 Watchers 0 Forks
Languages
Scala 99.8%
Verilog 0.2%
Powered by Gitea Version: 28.2.0 Page: 499ms Template: 188ms
Dark
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API