riscv/sifive-blocks
1
0
Fork 0
Code Releases Activity
Freedom RTL blocks (https://github.com/sifive/sifive-blocks)
112 Commits 1 Branch 0 Tags 280 KiB
Scala 99.8%
Verilog 0.2%
6a13639cf3
Go to file
Megan Wachs 6a13639cf3 SPI: Make it easier to build arbitrary bundles
2017-09-20 16:21:21 -07:00
src/main/scala SPI: Make it easier to build arbitrary bundles 2017-09-20 16:21:21 -07:00
vsrc Updates to go with the fpga-shells directory 2017-08-17 18:12:49 -07:00
.gitignore Add /target to .gitignore. 2016-11-30 13:29:54 -08:00
LICENSE Initial commit. 2016-11-29 04:08:44 -08:00