devices: add support for the chiplink protocol
This commit is contained in:
Wesley W. Terpstra
parent
48a9acc8a4
commit
3db375ef43
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@ -0,0 +1,93 @@
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// See LICENSE for license details.
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package sifive.blocks.devices.chiplink
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import Chisel._
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import freechips.rocketchip.util.{rightOR,GenericParameterizedBundle}
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class WideDataLayerPortLane(params: ChipLinkParams) extends GenericParameterizedBundle(params) {
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val clk = Clock(OUTPUT)
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val rst = Bool(OUTPUT)
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val send = Bool(OUTPUT)
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val data = UInt(OUTPUT, width=params.dataBits)
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}
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class WideDataLayerPort(params: ChipLinkParams) extends GenericParameterizedBundle(params) {
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val c2b = new WideDataLayerPortLane(params)
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val b2c = new WideDataLayerPortLane(params).flip
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}
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class DataLayer(params: ChipLinkParams) extends GenericParameterizedBundle(params) {
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val data = UInt(OUTPUT, width=params.dataBits)
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val last = Bool(OUTPUT)
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val beats = UInt(OUTPUT, width=params.xferBits + 1)
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}
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class CreditBump(params: ChipLinkParams) extends GenericParameterizedBundle(params) {
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val a = UInt(OUTPUT, width = params.creditBits)
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val b = UInt(OUTPUT, width = params.creditBits)
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val c = UInt(OUTPUT, width = params.creditBits)
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val d = UInt(OUTPUT, width = params.creditBits)
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val e = UInt(OUTPUT, width = params.creditBits)
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def X: Seq[UInt] = Seq(a, b, c, d, e)
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// saturating addition
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def +(that: CreditBump): CreditBump = {
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val out = Wire(new CreditBump(params))
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(out.X zip (X zip that.X)) foreach { case (o, (x, y)) =>
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val z = x +& y
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o := Mux((z >> params.creditBits).orR, ~UInt(0, width=params.creditBits), z)
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}
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out
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}
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// Send the MSB of the credits
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def toHeader: (UInt, CreditBump) = {
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def msb(x: UInt) = {
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val mask = rightOR(x) >> 1
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val msbOH = ~(~x | mask)
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val msb = OHToUInt(msbOH << 1, params.creditBits + 1) // 0 = 0, 1 = 1, 2 = 4, 3 = 8, ...
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val pad = (msb | UInt(0, width=5))(4,0)
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(pad, x & mask)
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}
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val (a_msb, a_rest) = msb(a)
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val (b_msb, b_rest) = msb(b)
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val (c_msb, c_rest) = msb(c)
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val (d_msb, d_rest) = msb(d)
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val (e_msb, e_rest) = msb(e)
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val header = Cat(
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e_msb, d_msb, c_msb, b_msb, a_msb,
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UInt(0, width = 4), // padding
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UInt(5, width = 3))
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val out = Wire(new CreditBump(params))
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out.a := a_rest
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out.b := b_rest
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out.c := c_rest
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out.d := d_rest
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out.e := e_rest
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(header, out)
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}
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}
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object CreditBump {
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def apply(params: ChipLinkParams, x: Int): CreditBump = {
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val v = UInt(x, width = params.creditBits)
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val out = Wire(new CreditBump(params))
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out.X.foreach { _ := v }
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out
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}
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def apply(params: ChipLinkParams, header: UInt): CreditBump = {
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def convert(x: UInt) =
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Mux(x > UInt(params.creditBits),
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~UInt(0, width = params.creditBits),
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UIntToOH(x, params.creditBits + 1) >> 1)
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val out = Wire(new CreditBump(params))
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out.a := convert(header(11, 7))
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out.b := convert(header(16, 12))
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out.c := convert(header(21, 17))
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out.d := convert(header(26, 22))
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out.e := convert(header(31, 27))
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out
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}
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}
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@ -0,0 +1,37 @@
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// See LICENSE for license details.
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package sifive.blocks.devices.chiplink
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import Chisel._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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class CAM(keys: Int, dataBits: Int) extends Module
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{
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val io = new Bundle {
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// alloc.valid => allocate a key
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// alloc.ready => a key is avilable
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val alloc = Decoupled(UInt(width = dataBits)).flip
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val key = UInt(OUTPUT, width = log2Ceil(keys))
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// free.valid => release the key
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val free = Valid(UInt(width = log2Ceil(keys))).flip
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val data = UInt(OUTPUT, width = dataBits)
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}
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val free = RegInit(UInt((BigInt(1) << keys) - 1, width = keys))
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val data = Mem(keys, UInt(width = dataBits))
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val free_sel = ~(leftOR(free, keys) << 1) & free
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io.key := OHToUInt(free_sel, keys)
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io.alloc.ready := free.orR
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when (io.alloc.fire()) { data.write(io.key, io.alloc.bits) }
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// Support free in same cycle as alloc
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val bypass = io.alloc.fire() && io.free.bits === io.key
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io.data := Mux(bypass, io.alloc.bits, data(io.free.bits))
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// Update CAM usage
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val clr = Mux(io.alloc.fire(), free_sel, UInt(0))
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val set = Mux(io.free.valid, UIntToOH(io.free.bits), UInt(0))
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free := (free & ~clr) | set
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}
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@ -0,0 +1,207 @@
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// See LICENSE for license details.
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package sifive.blocks.devices.chiplink
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.devices.tilelink.TLBusBypass
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import freechips.rocketchip.util._
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class ChipLink(val params: ChipLinkParams)(implicit p: Parameters) extends LazyModule() {
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val device = new SimpleBus("chiplink", Seq("sifive,chiplink"))
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private def maybeManager(x: Seq[AddressSet], f: Seq[AddressSet] => TLManagerParameters) =
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if (x.isEmpty) Nil else Seq(f(x))
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private val slaveNode = TLManagerNode(Seq(TLManagerPortParameters(
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managers =
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maybeManager(params.TLUH, a => TLManagerParameters(
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address = a,
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resources = device.ranges,
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regionType = RegionType.GET_EFFECTS,
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executable = true,
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supportsArithmetic = params.atomicXfer,
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supportsLogical = params.atomicXfer,
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supportsGet = params.fullXfer,
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supportsPutFull = params.fullXfer,
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supportsPutPartial = params.fullXfer,
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supportsHint = params.fullXfer,
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fifoId = Some(0))) ++
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maybeManager(params.TLC, a => TLManagerParameters(
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address = a,
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resources = device.ranges,
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regionType = RegionType.TRACKED,
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executable = true,
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supportsAcquireT = params.acqXfer,
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supportsAcquireB = params.acqXfer,
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supportsArithmetic = params.atomicXfer,
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supportsLogical = params.atomicXfer,
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supportsGet = params.fullXfer,
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supportsPutFull = params.fullXfer,
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supportsPutPartial = params.fullXfer,
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supportsHint = params.fullXfer,
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fifoId = Some(0))),
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beatBytes = 4,
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endSinkId = params.sinks,
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minLatency = params.latency)))
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// Masters 1+ require order; Master 0 is unordered and may cache
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private val masterNode = TLClientNode(Seq(TLClientPortParameters(
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clients = Seq.tabulate(params.domains) { i =>
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TLClientParameters(
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name = "ChipLink Domain #" + i,
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sourceId = IdRange(i*params.sourcesPerDomain, (i + 1)*params.sourcesPerDomain),
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requestFifo = i > 0,
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supportsProbe = if (i == 0) params.fullXfer else params.noXfer) },
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minLatency = params.latency)))
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private val bypass = LazyModule(new TLBusBypass(beatBytes = 4))
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slaveNode := bypass.node
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val node = NodeHandle(bypass.node, masterNode)
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// Exported memory map. Used when connecting VIP
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lazy val managers = masterNode.edges.out(0).manager.managers
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lazy val mmap = {
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val (tlc, tluh) = managers.partition(_.supportsAcquireB)
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params.copy(
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TLUH = AddressSet.unify(tluh.flatMap(_.address)),
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TLC = AddressSet.unify(tlc.flatMap(_.address)))
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}
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lazy val module = new LazyModuleImp(this) {
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val io = IO(new Bundle {
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val port = new WideDataLayerPort(params)
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val bypass = Bool(OUTPUT)
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// These are fed to port.c2b.{clk,rst} -- must be specified by creator
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val c2b_clk = Clock(INPUT)
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val c2b_rst = Bool(INPUT)
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})
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// Ensure downstream devices support our requirements
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val (in, edgeIn) = slaveNode.in(0)
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val (out, edgeOut) = masterNode.out(0)
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require (edgeIn.manager.beatBytes == 4)
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edgeOut.manager.requireFifo()
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edgeOut.manager.managers.foreach { m =>
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require (m.supportsGet.contains(params.fullXfer),
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s"ChipLink requires ${m.name} support ${params.fullXfer} Get, not ${m.supportsGet}")
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if (m.supportsPutFull) {
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require (m.supportsPutFull.contains(params.fullXfer),
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s"ChipLink requires ${m.name} support ${params.fullXfer} PutFill, not ${m.supportsPutFull}")
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// !!! argh. AHB devices can't: require (m.supportsPutPartial.contains(params.fullXfer),
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// s"ChipLink requires ${m.name} support ${params.fullXfer} PutPartial not ${m.supportsPutPartial}")
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require (m.supportsArithmetic.contains(params.atomicXfer),
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s"ChipLink requires ${m.name} support ${params.atomicXfer} Arithmetic, not ${m.supportsArithmetic}")
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require (m.supportsLogical.contains(params.atomicXfer),
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s"ChipLink requires ${m.name} support ${params.atomicXfer} Logical, not ${m.supportsLogical}")
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}
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require (m.supportsHint.contains(params.fullXfer),
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s"ChipLink requires ${m.name} support ${params.fullXfer} Hint, not ${m.supportsHint}")
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require (!m.supportsAcquireT || m.supportsAcquireT.contains(params.acqXfer),
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s"ChipLink requires ${m.name} support ${params.acqXfer} AcquireT, not ${m.supportsAcquireT}")
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require (!m.supportsAcquireB || m.supportsAcquireB.contains(params.acqXfer),
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s"ChipLink requires ${m.name} support ${params.acqXfer} AcquireB, not ${m.supportsAcquireB}")
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require (!m.supportsAcquireB || !m.supportsPutFull || m.supportsAcquireT,
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s"ChipLink requires ${m.name} to support AcquireT if it supports Put and AcquireB")
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}
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// Anything that is optional, must be supported by the error device (for redirect)
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val errorDevs = edgeOut.manager.managers.filter(_.nodePath.last.lazyModule.className == "TLError")
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require (!errorDevs.isEmpty, "There is no TLError reachable from ChipLink. One must be instantiated.")
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val errorDev = errorDevs.head
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require (errorDev.supportsPutFull.contains(params.fullXfer),
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s"ChipLink requires ${errorDev.name} support ${params.fullXfer} PutFill, not ${errorDev.supportsPutFull}")
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require (errorDev.supportsPutPartial.contains(params.fullXfer),
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s"ChipLink requires ${errorDev.name} support ${params.fullXfer} PutPartial not ${errorDev.supportsPutPartial}")
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require (errorDev.supportsArithmetic.contains(params.atomicXfer),
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s"ChipLink requires ${errorDev.name} support ${params.atomicXfer} Arithmetic, not ${errorDev.supportsArithmetic}")
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require (errorDev.supportsLogical.contains(params.atomicXfer),
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s"ChipLink requires ${errorDev.name} support ${params.atomicXfer} Logical, not ${errorDev.supportsLogical}")
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require (errorDev.supportsAcquireT.contains(params.acqXfer),
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s"ChipLink requires ${errorDev.name} support ${params.acqXfer} AcquireT, not ${errorDev.supportsAcquireT}")
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// At most one cache can master ChipLink
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require (edgeIn.client.clients.filter(_.supportsProbe).size <= 1,
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s"ChipLink supports at most one caching master, ${edgeIn.client.clients.filter(_.supportsProbe).map(_.name)}")
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// Construct the info needed by all submodules
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val info = ChipLinkInfo(params, edgeIn, edgeOut, errorDevs.head.address.head.base)
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val sinkA = Module(new SinkA(info))
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val sinkB = Module(new SinkB(info))
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val sinkC = Module(new SinkC(info))
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val sinkD = Module(new SinkD(info))
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val sinkE = Module(new SinkE(info))
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val sourceA = Module(new SourceA(info))
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val sourceB = Module(new SourceB(info))
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val sourceC = Module(new SourceC(info))
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val sourceD = Module(new SourceD(info))
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val sourceE = Module(new SourceE(info))
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val rx = Module(new RX(info))
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rx.clock := io.port.b2c.clk
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rx.reset := io.port.b2c.rst
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rx.io.b2c_data := io.port.b2c.data
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rx.io.b2c_send := io.port.b2c.send
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out.a <> sourceA.io.a
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in .b <> sourceB.io.b
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out.c <> sourceC.io.c
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in .d <> sourceD.io.d
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out.e <> sourceE.io.e
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sourceA.io.q <> FromAsyncBundle(rx.io.a)
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sourceB.io.q <> FromAsyncBundle(rx.io.b)
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sourceC.io.q <> FromAsyncBundle(rx.io.c)
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sourceD.io.q <> FromAsyncBundle(rx.io.d)
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sourceE.io.q <> FromAsyncBundle(rx.io.e)
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val tx = Module(new TX(info))
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io.port.c2b.data := tx.io.c2b_data
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io.port.c2b.send := tx.io.c2b_send
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sinkA.io.a <> in .a
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sinkB.io.b <> out.b
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sinkC.io.c <> in .c
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sinkD.io.d <> out.d
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sinkE.io.e <> in .e
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if (params.syncTX) {
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tx.io.sa <> sinkA.io.q
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tx.io.sb <> sinkB.io.q
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tx.io.sc <> sinkC.io.q
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tx.io.sd <> sinkD.io.q
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tx.io.se <> sinkE.io.q
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} else {
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tx.clock := io.port.c2b.clk
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tx.reset := io.port.c2b.rst
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tx.io.a <> ToAsyncBundle(sinkA.io.q, params.crossingDepth)
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tx.io.b <> ToAsyncBundle(sinkB.io.q, params.crossingDepth)
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tx.io.c <> ToAsyncBundle(sinkC.io.q, params.crossingDepth)
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tx.io.d <> ToAsyncBundle(sinkD.io.q, params.crossingDepth)
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tx.io.e <> ToAsyncBundle(sinkE.io.q, params.crossingDepth)
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}
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// Pass credits from RX to TX
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tx.io.rxc <> rx.io.rxc
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tx.io.txc <> rx.io.txc
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// Connect the CAM source pools
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sinkD.io.a_clSource := sourceA.io.d_clSource
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sourceA.io.d_tlSource := sinkD.io.a_tlSource
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sinkD.io.c_clSource := sourceC.io.d_clSource
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sourceC.io.d_tlSource := sinkD.io.c_tlSource
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sourceD.io.e_tlSink := sinkE.io.d_tlSink
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sinkE.io.d_clSink := sourceD.io.e_clSink
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// Create the TX clock domain from input
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io.port.c2b.clk := io.c2b_clk
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io.port.c2b.rst := io.c2b_rst
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// Disable ChipLink while RX+TX are in reset
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val do_bypass = ResetCatchAndSync(clock, rx.reset) || ResetCatchAndSync(clock, tx.reset)
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bypass.module.io.bypass := do_bypass
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io.bypass := do_bypass
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}
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}
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@ -0,0 +1,137 @@
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// See LICENSE for license details.
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package sifive.blocks.devices.chiplink
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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case class ChipLinkParams(TLUH: Seq[AddressSet], TLC: Seq[AddressSet], sourceBits: Int = 6, sinkBits: Int = 5, syncTX: Boolean = false)
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{
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val domains = 8 // hard-wired into chiplink protocol
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require (sourceBits >= log2Ceil(domains))
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require (sinkBits >= 0)
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val sources = 1 << sourceBits
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val sinks = 1 << sinkBits
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val sourcesPerDomain = sources / domains
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val latency = 8 // ChipLink has at least 4 cycles of synchronization per side
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val dataBytes = 4
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val dataBits = dataBytes*8
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val clSourceBits = 16
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val clSinkBits = 16
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val crossingDepth = 8
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val Qdepth = 8192 / dataBytes
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val maxXfer = 4096
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val xferBits = log2Ceil(maxXfer)
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val creditBits = 20 // use saturating addition => we can exploit at most 1MB of buffers
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val addressBits = 64
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require (log2Ceil(Qdepth + 1) <= creditBits)
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// Protocol supported operations:
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val noXfer = TransferSizes.none
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val fullXfer = TransferSizes(1, 64) // !!! 4096)
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val acqXfer = TransferSizes(64, 64)
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val atomicXfer = TransferSizes(1, 8)
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}
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case object ChipLinkKey extends Field[Seq[ChipLinkParams]]
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case class TXN(domain: Int, source: Int)
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case class ChipLinkInfo(params: ChipLinkParams, edgeIn: TLEdge, edgeOut: TLEdge, errorDev: BigInt)
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{
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// TL source => CL TXN
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val sourceMap: Map[Int, TXN] = {
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var alloc = 1
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val domains = Array.fill(params.domains) { 0 }
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println("ChipLink source mapping CLdomain CLsource <= TLsource:")
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val out = Map() ++ edgeIn.client.clients.flatMap { c =>
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// If the client needs order, pick a domain for it
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val domain = if (c.requestFifo) alloc else 0
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val offset = domains(domain)
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println(s"\t${domain} [${offset}, ${offset + c.sourceId.size}) <= [${c.sourceId.start}, ${c.sourceId.end}):\t${c.name}")
|
||||
if (c.requestFifo) {
|
||||
alloc = alloc + 1
|
||||
if (alloc == params.domains) alloc = 1
|
||||
}
|
||||
c.sourceId.range.map { id =>
|
||||
val source = domains(domain)
|
||||
domains(domain) = source + 1
|
||||
(id, TXN(domain, source))
|
||||
}
|
||||
}
|
||||
println("")
|
||||
out
|
||||
}
|
||||
|
||||
def mux(m: Map[Int, Int]): Vec[UInt] = {
|
||||
val maxKey = m.keys.max
|
||||
val maxVal = m.values.max
|
||||
val valBits = log2Up(maxVal + 1)
|
||||
val out = Wire(Vec(maxKey + 1, UInt(width = valBits)))
|
||||
m.foreach { case (k, v) => out(k) := UInt(v, width = valBits) }
|
||||
out
|
||||
}
|
||||
|
||||
// Packet format; little-endian
|
||||
def encode(format: UInt, opcode: UInt, param: UInt, size: UInt, domain: UInt, source: UInt): UInt = {
|
||||
def fmt(x: UInt, w: Int) = (x | UInt(0, width=w))(w-1, 0)
|
||||
Cat(
|
||||
fmt(source, 16),
|
||||
fmt(domain, 3),
|
||||
fmt(size, 4),
|
||||
fmt(param, 3),
|
||||
fmt(opcode, 3),
|
||||
fmt(format, 3))
|
||||
}
|
||||
|
||||
def decode(x: UInt): Seq[UInt] = {
|
||||
val format = x( 2, 0)
|
||||
val opcode = x( 5, 3)
|
||||
val param = x( 8, 6)
|
||||
val size = x(12, 9)
|
||||
val domain = x(15, 13)
|
||||
val source = x(31, 16)
|
||||
Seq(format, opcode, param, size, domain, source)
|
||||
}
|
||||
|
||||
def size2beats(size: UInt): UInt = {
|
||||
val shift = log2Ceil(params.dataBytes)
|
||||
Cat(UIntToOH(size|UInt(0, width=4), params.xferBits + 1) >> (shift + 1), size <= UInt(shift))
|
||||
}
|
||||
|
||||
def mask2beats(size: UInt): UInt = {
|
||||
val shift = log2Ceil(params.dataBytes*8)
|
||||
Cat(UIntToOH(size|UInt(0, width=4), params.xferBits + 1) >> (shift + 1), size <= UInt(shift))
|
||||
}
|
||||
|
||||
def beats1(x: UInt, forceFormat: Option[UInt] = None): UInt = {
|
||||
val Seq(format, opcode, _, size, _, _) = decode(x)
|
||||
val beats = size2beats(size)
|
||||
val masks = mask2beats(size)
|
||||
val grant = opcode === TLMessages.Grant || opcode === TLMessages.GrantData
|
||||
val partial = opcode === TLMessages.PutPartialData
|
||||
val a = Mux(opcode(2), UInt(0), beats) + UInt(2) + Mux(partial, masks, UInt(0))
|
||||
val b = Mux(opcode(2), UInt(0), beats) + UInt(2) + Mux(partial, masks, UInt(0))
|
||||
val c = Mux(opcode(0), beats, UInt(0)) + UInt(2)
|
||||
val d = Mux(opcode(0), beats, UInt(0)) + grant.asUInt
|
||||
val e = UInt(0)
|
||||
val f = UInt(0)
|
||||
Vec(a, b, c, d, e, f)(forceFormat.getOrElse(format))
|
||||
}
|
||||
|
||||
def firstlast(x: DecoupledIO[UInt], forceFormat: Option[UInt] = None): (Bool, Bool) = {
|
||||
val count = RegInit(UInt(0))
|
||||
val beats = beats1(x.bits, forceFormat)
|
||||
val first = count === UInt(0)
|
||||
val last = count === UInt(1) || (first && beats === UInt(0))
|
||||
when (x.fire()) { count := Mux(first, beats, count - UInt(1)) }
|
||||
(first, last)
|
||||
}
|
||||
|
||||
// You can't just unilaterally use error, because this would misalign the mask
|
||||
def makeError(legal: Bool, address: UInt): UInt =
|
||||
Cat(
|
||||
Mux(legal, address, UInt(errorDev))(params.addressBits-1, log2Ceil(params.maxXfer)),
|
||||
address(log2Ceil(params.maxXfer)-1, 0))
|
||||
}
|
||||
|
|
@ -0,0 +1,106 @@
|
|||
// See LICENSE for license details.
|
||||
package sifive.blocks.devices.chiplink
|
||||
|
||||
import Chisel._
|
||||
import freechips.rocketchip.tilelink._
|
||||
import freechips.rocketchip.util._
|
||||
|
||||
class ParitalExtractor[T <: TLDataChannel](gen: T) extends Module
|
||||
{
|
||||
val io = new Bundle {
|
||||
val last = Bool(INPUT)
|
||||
val i = Decoupled(gen).flip
|
||||
val o = Decoupled(gen)
|
||||
}
|
||||
|
||||
io.o <> io.i
|
||||
|
||||
// Grab references to the fields we care about
|
||||
val (i_opcode, i_data) = io.i.bits match {
|
||||
case a: TLBundleA => (a.opcode, a.data)
|
||||
case b: TLBundleB => (b.opcode, b.data)
|
||||
}
|
||||
val (o_data, o_mask) = io.o.bits match {
|
||||
case a: TLBundleA => (a.data, a.mask)
|
||||
case b: TLBundleB => (b.data, b.mask)
|
||||
}
|
||||
|
||||
val state = RegInit(UInt(0, width=4)) // number of nibbles; [0,8]
|
||||
val shift = Reg(UInt(width=32))
|
||||
val enable = i_opcode === TLMessages.PutPartialData
|
||||
val empty = state === UInt(0)
|
||||
|
||||
when (enable) {
|
||||
val wide = shift | (i_data << (state << 2))
|
||||
o_data := Vec.tabulate(4) { i => wide(9*(i+1)-1, 9*i+1) } .asUInt
|
||||
o_mask := Vec.tabulate(4) { i => wide(9*i) } .asUInt
|
||||
|
||||
// Swallow beat if we have no nibbles
|
||||
when (empty) {
|
||||
io.i.ready := Bool(true)
|
||||
io.o.valid := Bool(false)
|
||||
}
|
||||
|
||||
// Update the FSM
|
||||
when (io.i.fire()) {
|
||||
shift := Mux(empty, i_data, wide >> 36)
|
||||
state := state - UInt(1)
|
||||
when (empty) { state := UInt(8) }
|
||||
when (io.last) { state := UInt(0) }
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
class PartialInjector[T <: TLDataChannel](gen: T) extends Module
|
||||
{
|
||||
val io = new Bundle {
|
||||
val i_last = Bool(INPUT)
|
||||
val o_last = Bool(OUTPUT)
|
||||
val i = Decoupled(gen).flip
|
||||
val o = Decoupled(gen)
|
||||
}
|
||||
|
||||
io.o <> io.i
|
||||
|
||||
// Grab references to the fields we care about
|
||||
val (i_opcode, i_data, i_mask) = io.i.bits match {
|
||||
case a: TLBundleA => (a.opcode, a.data, a.mask)
|
||||
case b: TLBundleB => (b.opcode, b.data, b.mask)
|
||||
}
|
||||
val o_data = io.o.bits match {
|
||||
case a: TLBundleA => a.data
|
||||
case b: TLBundleB => b.data
|
||||
}
|
||||
|
||||
val state = RegInit(UInt(0, width=4)) // number of nibbles; [0,8]
|
||||
val shift = RegInit(UInt(0, width=32))
|
||||
val full = state(3)
|
||||
val partial = i_opcode === TLMessages.PutPartialData
|
||||
|
||||
val last = RegInit(Bool(false))
|
||||
io.o_last := Mux(partial, last, io.i_last)
|
||||
|
||||
when (partial) {
|
||||
val bytes = Seq.tabulate(4) { i => i_data(8*(i+1)-1, 8*i) }
|
||||
val bits = i_mask.toBools
|
||||
val mixed = Cat(Seq(bits, bytes).transpose.flatten.reverse)
|
||||
val wide = shift | (mixed << (state << 2))
|
||||
o_data := wide
|
||||
|
||||
// Inject a beat
|
||||
when ((io.i_last || full) && !last) {
|
||||
io.i.ready := Bool(false)
|
||||
}
|
||||
|
||||
// Update the FSM
|
||||
when (io.o.fire()) {
|
||||
shift := wide >> 32
|
||||
state := state + UInt(1)
|
||||
when (full || last) {
|
||||
state := UInt(0)
|
||||
shift := UInt(0)
|
||||
}
|
||||
last := io.i_last && !last
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,90 @@
|
|||
// See LICENSE for license details.
|
||||
package sifive.blocks.devices.chiplink
|
||||
|
||||
import Chisel._
|
||||
import freechips.rocketchip.tilelink._
|
||||
import freechips.rocketchip.util._
|
||||
|
||||
class RX(info: ChipLinkInfo) extends Module
|
||||
{
|
||||
val io = new Bundle {
|
||||
val b2c_send = Bool(INPUT)
|
||||
val b2c_data = UInt(INPUT, info.params.dataBits)
|
||||
val a = new AsyncBundle(info.params.crossingDepth, UInt(width = info.params.dataBits))
|
||||
val b = new AsyncBundle(info.params.crossingDepth, UInt(width = info.params.dataBits))
|
||||
val c = new AsyncBundle(info.params.crossingDepth, UInt(width = info.params.dataBits))
|
||||
val d = new AsyncBundle(info.params.crossingDepth, UInt(width = info.params.dataBits))
|
||||
val e = new AsyncBundle(info.params.crossingDepth, UInt(width = info.params.dataBits))
|
||||
val rxc = new AsyncBundle(1, new CreditBump(info.params))
|
||||
val txc = new AsyncBundle(1, new CreditBump(info.params))
|
||||
}
|
||||
|
||||
// Immediately register our input data
|
||||
val b2c_data = RegNext(RegNext(io.b2c_data))
|
||||
val b2c_send = RegNext(RegNext(io.b2c_send, Bool(false)), Bool(false))
|
||||
|
||||
// Fit b2c into the firstlast API
|
||||
val beat = Wire(Decoupled(UInt(width = info.params.dataBits)))
|
||||
beat.bits := b2c_data
|
||||
beat.valid := b2c_send
|
||||
beat.ready := Bool(true)
|
||||
|
||||
// Select the correct HellaQueue for the request
|
||||
val (first, _) = info.firstlast(beat)
|
||||
val formatBits = beat.bits(2, 0)
|
||||
val formatValid = beat.fire() && first
|
||||
val format = Mux(formatValid, formatBits, RegEnable(formatBits, formatValid))
|
||||
val formatOH = UIntToOH(format)
|
||||
|
||||
// Create the receiver buffers
|
||||
val hqa = Module(new HellaQueue(info.params.Qdepth)(beat.bits))
|
||||
val hqb = Module(new HellaQueue(info.params.Qdepth)(beat.bits))
|
||||
val hqc = Module(new HellaQueue(info.params.Qdepth)(beat.bits))
|
||||
val hqd = Module(new HellaQueue(info.params.Qdepth)(beat.bits))
|
||||
val hqe = Module(new HellaQueue(info.params.Qdepth)(beat.bits))
|
||||
|
||||
// Use these to save some typing; function to prevent renaming
|
||||
private def hqX = Seq(hqa, hqb, hqc, hqd, hqe)
|
||||
private def ioX = Seq(io.a, io.b, io.c, io.d, io.e)
|
||||
|
||||
// Enqueue to the HellaQueues
|
||||
(formatOH.toBools zip hqX) foreach { case (sel, hq) =>
|
||||
hq.io.enq.valid := beat.valid && sel
|
||||
hq.io.enq.bits := beat.bits
|
||||
assert (!hq.io.enq.valid || hq.io.enq.ready) // overrun impossible
|
||||
}
|
||||
|
||||
// Send HellaQueue output to their respective FSMs
|
||||
(hqX zip ioX) foreach { case (hq, io) =>
|
||||
io <> ToAsyncBundle(hq.io.deq, info.params.crossingDepth)
|
||||
}
|
||||
|
||||
// Credits we need to hand-off to the TX FSM
|
||||
val tx = RegInit(CreditBump(info.params, 0))
|
||||
val rx = RegInit(CreditBump(info.params, info.params.Qdepth))
|
||||
|
||||
// Constantly transmit credit updates
|
||||
val txOut = Wire(Decoupled(new CreditBump(info.params)))
|
||||
val rxOut = Wire(Decoupled(new CreditBump(info.params)))
|
||||
txOut.valid := Bool(true)
|
||||
rxOut.valid := Bool(true)
|
||||
txOut.bits := tx
|
||||
rxOut.bits := rx
|
||||
io.txc <> ToAsyncBundle(txOut, 1)
|
||||
io.rxc <> ToAsyncBundle(rxOut, 1)
|
||||
|
||||
// Generate new RX credits as the HellaQueues drain
|
||||
val rxInc = Wire(new CreditBump(info.params))
|
||||
(hqX zip rxInc.X) foreach { case (hq, inc) =>
|
||||
inc := hq.io.deq.fire().asUInt
|
||||
}
|
||||
|
||||
// Generate new TX credits as we receive F-format messages
|
||||
val txInc = Mux(beat.valid && formatOH(5), CreditBump(info.params, beat.bits), CreditBump(info.params, 0))
|
||||
|
||||
// As we hand-over credits, reset the counters
|
||||
tx := tx + txInc
|
||||
rx := rx + rxInc
|
||||
when (txOut.fire()) { tx := txInc }
|
||||
when (rxOut.fire()) { rx := rxInc }
|
||||
}
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
// See LICENSE for license details.
|
||||
package sifive.blocks.devices.chiplink
|
||||
|
||||
import Chisel._
|
||||
import freechips.rocketchip.tilelink._
|
||||
|
||||
class SinkA(info: ChipLinkInfo) extends Module
|
||||
{
|
||||
val io = new Bundle {
|
||||
val a = Decoupled(new TLBundleA(info.edgeIn.bundle)).flip
|
||||
val q = Decoupled(new DataLayer(info.params))
|
||||
}
|
||||
|
||||
// Map TileLink sources to ChipLink sources+domain
|
||||
val tl2cl = info.sourceMap
|
||||
val source = info.mux(tl2cl.mapValues(_.source))
|
||||
val domain = info.mux(tl2cl.mapValues(_.domain))
|
||||
|
||||
// We need a Q because we stall the channel while serializing it's header
|
||||
val inject = Module(new PartialInjector(io.a.bits))
|
||||
inject.io.i <> Queue(io.a, 1, flow=true)
|
||||
inject.io.i_last := info.edgeIn.last(inject.io.i)
|
||||
val a = inject.io.o
|
||||
val a_last = inject.io.o_last
|
||||
val a_hasData = info.edgeIn.hasData(a.bits)
|
||||
val a_partial = a.bits.opcode === TLMessages.PutPartialData
|
||||
|
||||
// A simple FSM to generate the packet components
|
||||
val state = RegInit(UInt(0, width = 2))
|
||||
val s_header = UInt(0, width = 2)
|
||||
val s_address0 = UInt(1, width = 2)
|
||||
val s_address1 = UInt(2, width = 2)
|
||||
val s_data = UInt(3, width = 2)
|
||||
|
||||
when (io.q.fire()) {
|
||||
switch (state) {
|
||||
is (s_header) { state := s_address0 }
|
||||
is (s_address0) { state := s_address1 }
|
||||
is (s_address1) { state := Mux(a_hasData, s_data, s_header) }
|
||||
is (s_data) { state := Mux(!a_last, s_data, s_header) }
|
||||
}
|
||||
}
|
||||
|
||||
// Construct the header beat
|
||||
val header = info.encode(
|
||||
format = UInt(0),
|
||||
opcode = a.bits.opcode,
|
||||
param = a.bits.param,
|
||||
size = a.bits.size,
|
||||
domain = domain(a.bits.source),
|
||||
source = source(a.bits.source))
|
||||
|
||||
// Construct the address beats
|
||||
val address0 = a.bits.address
|
||||
val address1 = a.bits.address >> 32
|
||||
|
||||
// Frame the output packet
|
||||
val isLastState = state === Mux(a_hasData, s_data, s_address1)
|
||||
a.ready := io.q.ready && isLastState
|
||||
io.q.valid := a.valid
|
||||
io.q.bits.last := a_last && isLastState
|
||||
io.q.bits.data := Vec(header, address0, address1, a.bits.data)(state)
|
||||
io.q.bits.beats := Mux(a_hasData, info.size2beats(a.bits.size), UInt(0)) + UInt(3) +
|
||||
Mux(a_partial, info.mask2beats(a.bits.size), UInt(0))
|
||||
}
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
// See LICENSE for license details.
|
||||
package sifive.blocks.devices.chiplink
|
||||
|
||||
import Chisel._
|
||||
import freechips.rocketchip.tilelink._
|
||||
|
||||
class SinkB(info: ChipLinkInfo) extends Module
|
||||
{
|
||||
val io = new Bundle {
|
||||
val b = Decoupled(new TLBundleB(info.edgeOut.bundle)).flip
|
||||
val q = Decoupled(new DataLayer(info.params))
|
||||
}
|
||||
|
||||
// We need a Q because we stall the channel while serializing it's header
|
||||
val inject = Module(new PartialInjector(io.b.bits))
|
||||
inject.io.i <> Queue(io.b, 1, flow=true)
|
||||
inject.io.i_last := info.edgeOut.last(inject.io.i)
|
||||
val b = inject.io.o
|
||||
val b_last = inject.io.o_last
|
||||
val b_hasData = info.edgeOut.hasData(b.bits)
|
||||
val b_partial = b.bits.opcode === TLMessages.PutPartialData
|
||||
|
||||
// A simple FSM to generate the packet components
|
||||
val state = RegInit(UInt(0, width = 2))
|
||||
val s_header = UInt(0, width = 2)
|
||||
val s_address0 = UInt(1, width = 2)
|
||||
val s_address1 = UInt(2, width = 2)
|
||||
val s_data = UInt(3, width = 2)
|
||||
|
||||
when (io.q.fire()) {
|
||||
switch (state) {
|
||||
is (s_header) { state := s_address0 }
|
||||
is (s_address0) { state := s_address1 }
|
||||
is (s_address1) { state := Mux(b_hasData, s_data, s_header) }
|
||||
is (s_data) { state := Mux(!b_last, s_data, s_header) }
|
||||
}
|
||||
}
|
||||
|
||||
// Construct the header beat
|
||||
val header = info.encode(
|
||||
format = UInt(1),
|
||||
opcode = b.bits.opcode,
|
||||
param = b.bits.param,
|
||||
size = b.bits.size,
|
||||
domain = UInt(0), // ChipLink only allows one remote cache, in domain 0
|
||||
source = UInt(0))
|
||||
|
||||
assert (!b.valid || b.bits.source === UInt(0))
|
||||
|
||||
// Construct the address beats
|
||||
val address0 = b.bits.address
|
||||
val address1 = b.bits.address >> 32
|
||||
|
||||
// Frame the output packet
|
||||
val isLastState = state === Mux(b_hasData, s_data, s_address1)
|
||||
b.ready := io.q.ready && isLastState
|
||||
io.q.valid := b.valid
|
||||
io.q.bits.last := b_last && isLastState
|
||||
io.q.bits.data := Vec(header, address0, address1, b.bits.data)(state)
|
||||
io.q.bits.beats := Mux(b_hasData, info.size2beats(b.bits.size), UInt(0)) + UInt(3) +
|
||||
Mux(b_partial, info.mask2beats(b.bits.size), UInt(0))
|
||||
}
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
// See LICENSE for license details.
|
||||
package sifive.blocks.devices.chiplink
|
||||
|
||||
import Chisel._
|
||||
import freechips.rocketchip.tilelink._
|
||||
|
||||
class SinkC(info: ChipLinkInfo) extends Module
|
||||
{
|
||||
val io = new Bundle {
|
||||
val c = Decoupled(new TLBundleC(info.edgeIn.bundle)).flip
|
||||
val q = Decoupled(new DataLayer(info.params))
|
||||
}
|
||||
|
||||
// Map TileLink sources to ChipLink sources+domain
|
||||
val tl2cl = info.sourceMap
|
||||
val source = info.mux(tl2cl.mapValues(_.source))
|
||||
val domain = info.mux(tl2cl.mapValues(_.domain))
|
||||
|
||||
// We need a Q because we stall the channel while serializing it's header
|
||||
val c = Queue(io.c, 1, flow=true)
|
||||
val c_last = info.edgeIn.last(c)
|
||||
val c_hasData = info.edgeIn.hasData(c.bits)
|
||||
val c_release = c.bits.opcode === TLMessages.Release || c.bits.opcode === TLMessages.ReleaseData
|
||||
|
||||
// A simple FSM to generate the packet components
|
||||
val state = RegInit(UInt(0, width = 2))
|
||||
val s_header = UInt(0, width = 2)
|
||||
val s_address0 = UInt(1, width = 2)
|
||||
val s_address1 = UInt(2, width = 2)
|
||||
val s_data = UInt(3, width = 2)
|
||||
|
||||
when (io.q.fire()) {
|
||||
switch (state) {
|
||||
is (s_header) { state := s_address0 }
|
||||
is (s_address0) { state := s_address1 }
|
||||
is (s_address1) { state := Mux(c_hasData, s_data, s_header) }
|
||||
is (s_data) { state := Mux(!c_last, s_data, s_header) }
|
||||
}
|
||||
}
|
||||
|
||||
// Construct the header beat
|
||||
val header = info.encode(
|
||||
format = UInt(2),
|
||||
opcode = c.bits.opcode,
|
||||
param = c.bits.param,
|
||||
size = c.bits.size,
|
||||
domain = UInt(0), // only caches (unordered) can release
|
||||
source = Mux(c_release, source(c.bits.source), UInt(0)))
|
||||
|
||||
assert (!c.valid || domain(c.bits.source) === UInt(0))
|
||||
|
||||
// Construct the address beats
|
||||
val address0 = c.bits.address
|
||||
val address1 = c.bits.address >> 32
|
||||
|
||||
// Frame the output packet
|
||||
val isLastState = state === Mux(c_hasData, s_data, s_address1)
|
||||
c.ready := io.q.ready && isLastState
|
||||
io.q.valid := c.valid
|
||||
io.q.bits.last := c_last && isLastState
|
||||
io.q.bits.data := Vec(header, address0, address1, c.bits.data)(state)
|
||||
io.q.bits.beats := Mux(c_hasData, info.size2beats(c.bits.size), UInt(0)) + UInt(3)
|
||||
}
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
// See LICENSE for license details.
|
||||
package sifive.blocks.devices.chiplink
|
||||
|
||||
import Chisel._
|
||||
import freechips.rocketchip.tilelink._
|
||||
|
||||
class SinkD(info: ChipLinkInfo) extends Module
|
||||
{
|
||||
val io = new Bundle {
|
||||
val d = Decoupled(new TLBundleD(info.edgeOut.bundle)).flip
|
||||
val q = Decoupled(new DataLayer(info.params))
|
||||
val a_tlSource = Valid(UInt(width = info.params.sourceBits))
|
||||
val a_clSource = UInt(INPUT, width = info.params.clSourceBits)
|
||||
val c_tlSource = Valid(UInt(width = info.params.sourceBits))
|
||||
val c_clSource = UInt(INPUT, width = info.params.clSourceBits)
|
||||
}
|
||||
|
||||
// The FSM states
|
||||
val state = RegInit(UInt(0, width = 2))
|
||||
val s_header = UInt(0, width = 2)
|
||||
val s_sink = UInt(1, width = 2)
|
||||
val s_data = UInt(2, width = 2)
|
||||
|
||||
// We need a Q because we stall the channel while serializing it's header
|
||||
val d = Queue(io.d, 1, flow=true)
|
||||
val d_last = info.edgeOut.last(d)
|
||||
val d_hasData = info.edgeOut.hasData(d.bits)
|
||||
val d_grant = d.bits.opcode === TLMessages.Grant || d.bits.opcode === TLMessages.GrantData
|
||||
|
||||
when (io.q.fire()) {
|
||||
switch (state) {
|
||||
is (s_header) { state := Mux(d_grant, s_sink, Mux(d_hasData, s_data, s_header)) }
|
||||
is (s_sink) { state := Mux(d_hasData, s_data, s_header) }
|
||||
is (s_data) { state := Mux(d_last, s_header, s_data) }
|
||||
}
|
||||
}
|
||||
|
||||
// Release the TL source
|
||||
val relack = d.bits.opcode === TLMessages.ReleaseAck
|
||||
io.a_tlSource.valid := io.q.fire() && state === s_header && !relack
|
||||
io.a_tlSource.bits := d.bits.source
|
||||
io.c_tlSource.valid := io.q.fire() && state === s_header && relack
|
||||
io.c_tlSource.bits := d.bits.source
|
||||
|
||||
// Construct the header beat
|
||||
val header = info.encode(
|
||||
format = UInt(3),
|
||||
opcode = d.bits.opcode,
|
||||
param = d.bits.param,
|
||||
size = d.bits.size,
|
||||
domain = d.bits.source >> log2Ceil(info.params.sourcesPerDomain),
|
||||
source = Mux(relack, io.c_clSource, io.a_clSource))
|
||||
|
||||
val isLastState = state === Mux(d_hasData, s_data, Mux(d_grant, s_sink, s_header))
|
||||
d.ready := io.q.ready && isLastState
|
||||
io.q.valid := d.valid
|
||||
io.q.bits.last := d_last && isLastState
|
||||
io.q.bits.data := Vec(header, d.bits.sink, d.bits.data)(state)
|
||||
io.q.bits.beats := Mux(d_hasData, info.size2beats(d.bits.size), UInt(0)) + UInt(1) + d_grant.asUInt
|
||||
}
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
// See LICENSE for license details.
|
||||
package sifive.blocks.devices.chiplink
|
||||
|
||||
import Chisel._
|
||||
import freechips.rocketchip.tilelink._
|
||||
|
||||
class SinkE(info: ChipLinkInfo) extends Module
|
||||
{
|
||||
val io = new Bundle {
|
||||
val e = Decoupled(new TLBundleE(info.edgeIn.bundle)).flip
|
||||
val q = Decoupled(new DataLayer(info.params))
|
||||
// Find the sink from D
|
||||
val d_tlSink = Valid(UInt(width = info.params.sinkBits))
|
||||
val d_clSink = UInt(INPUT, width = info.params.clSinkBits)
|
||||
}
|
||||
|
||||
io.d_tlSink.valid := io.e.fire()
|
||||
io.d_tlSink.bits := io.e.bits.sink
|
||||
|
||||
val header = info.encode(
|
||||
format = UInt(4),
|
||||
opcode = UInt(0),
|
||||
param = UInt(0),
|
||||
size = UInt(0),
|
||||
domain = UInt(0),
|
||||
source = io.d_clSink)
|
||||
|
||||
io.e.ready := io.q.ready
|
||||
io.q.valid := io.e.valid
|
||||
io.q.bits.last := Bool(true)
|
||||
io.q.bits.data := header
|
||||
io.q.bits.beats := UInt(1)
|
||||
}
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
// See LICENSE for license details.
|
||||
package sifive.blocks.devices.chiplink
|
||||
|
||||
import Chisel._
|
||||
import freechips.rocketchip.tilelink._
|
||||
import freechips.rocketchip.util._
|
||||
|
||||
class SourceA(info: ChipLinkInfo) extends Module
|
||||
{
|
||||
val io = new Bundle {
|
||||
val a = Decoupled(new TLBundleA(info.edgeOut.bundle))
|
||||
val q = Decoupled(UInt(width = info.params.dataBits)).flip
|
||||
// Used by D to find the txn
|
||||
val d_tlSource = Valid(UInt(width = info.params.sourceBits)).flip
|
||||
val d_clSource = UInt(OUTPUT, width = info.params.clSourceBits)
|
||||
}
|
||||
|
||||
// CAM of sources used for each domain
|
||||
val cams = Seq.fill(info.params.domains) {
|
||||
Module(new CAM(info.params.sourcesPerDomain, info.params.clSourceBits))
|
||||
}
|
||||
|
||||
// A simple FSM to generate the packet components
|
||||
val state = RegInit(UInt(0, width = 2))
|
||||
val s_header = UInt(0, width = 2)
|
||||
val s_address0 = UInt(1, width = 2)
|
||||
val s_address1 = UInt(2, width = 2)
|
||||
val s_data = UInt(3, width = 2)
|
||||
|
||||
private def hold(key: UInt)(data: UInt) = {
|
||||
val enable = state === key
|
||||
Mux(enable, data, RegEnable(data, enable))
|
||||
}
|
||||
|
||||
// Extract header fields
|
||||
val Seq(_, q_opcode, q_param, q_size, q_domain, q_source) =
|
||||
info.decode(io.q.bits).map(hold(s_header) _)
|
||||
|
||||
// Latch address
|
||||
val q_address0 = hold(s_address0)(io.q.bits)
|
||||
val q_address1 = hold(s_address1)(io.q.bits)
|
||||
|
||||
val (_, q_last) = info.firstlast(io.q, Some(UInt(0)))
|
||||
val q_hasData = !q_opcode(2)
|
||||
val a_first = RegEnable(state =/= s_data, io.q.fire())
|
||||
|
||||
when (io.q.fire()) {
|
||||
switch (state) {
|
||||
is (s_header) { state := s_address0 }
|
||||
is (s_address0) { state := s_address1 }
|
||||
is (s_address1) { state := Mux(q_hasData, s_data, s_header) }
|
||||
is (s_data) { state := Mux(!q_last, s_data, s_header) }
|
||||
}
|
||||
}
|
||||
|
||||
// Determine if the request is legal. If not, route to error device.
|
||||
val q_address = Cat(q_address1, q_address0)
|
||||
val q_acq = q_opcode === TLMessages.AcquireBlock || q_opcode === TLMessages.AcquirePerm
|
||||
val q_write = Mux(q_acq, q_param === TLPermissions.NtoT || q_param === TLPermissions.BtoT, q_hasData)
|
||||
val exists = info.edgeOut.manager.containsSafe(q_address)
|
||||
private def writeable(m: TLManagerParameters): Boolean = if (m.supportsAcquireB) m.supportsAcquireT else m.supportsPutFull
|
||||
private def acquireable(m: TLManagerParameters): Boolean = m.supportsAcquireB || m.supportsAcquireT
|
||||
private def toBool(x: Boolean) = Bool(x)
|
||||
val writeOk = info.edgeOut.manager.fastProperty(q_address, writeable, toBool)
|
||||
val acquireOk = info.edgeOut.manager.fastProperty(q_address, acquireable, toBool)
|
||||
val q_legal = exists && (!q_write || writeOk) && (!q_acq || acquireOk)
|
||||
|
||||
// Look for an available source in the correct domain
|
||||
val source_ok = Vec(cams.map(_.io.alloc.ready))(q_domain)
|
||||
val source = Vec(cams.map(_.io.key))(q_domain) holdUnless a_first
|
||||
val a_sel = UIntToOH(q_domain)
|
||||
|
||||
// Feed our preliminary A channel via the Partial Extractor FSM
|
||||
val extract = Module(new ParitalExtractor(io.a.bits))
|
||||
io.a <> extract.io.o
|
||||
val a = extract.io.i
|
||||
extract.io.last := q_last
|
||||
|
||||
a.bits.opcode := q_opcode
|
||||
a.bits.param := q_param
|
||||
a.bits.size := q_size
|
||||
a.bits.source := Cat(q_domain, source)
|
||||
a.bits.address := info.makeError(q_legal, q_address)
|
||||
a.bits.mask := MaskGen(q_address0, q_size, info.params.dataBytes)
|
||||
a.bits.data := io.q.bits
|
||||
|
||||
val stall = a_first && !source_ok
|
||||
val xmit = q_last || state === s_data
|
||||
a.valid := (io.q.valid && !stall) && xmit
|
||||
io.q.ready := (a.ready && !stall) || !xmit
|
||||
(cams zip a_sel.toBools) foreach { case (cam, sel) =>
|
||||
cam.io.alloc.valid := sel && a_first && xmit && io.q.valid && a.ready
|
||||
cam.io.alloc.bits := q_source
|
||||
}
|
||||
|
||||
// Free the CAM entries
|
||||
val d_clDomain = io.d_tlSource.bits >> log2Ceil(info.params.sourcesPerDomain)
|
||||
val d_sel = UIntToOH(d_clDomain)
|
||||
io.d_clSource := Vec(cams.map(_.io.data))(d_clDomain)
|
||||
(cams zip d_sel.toBools) foreach { case (cam, sel) =>
|
||||
cam.io.free.bits := io.d_tlSource.bits
|
||||
cam.io.free.valid := io.d_tlSource.valid && sel
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
// See LICENSE for license details.
|
||||
package sifive.blocks.devices.chiplink
|
||||
|
||||
import Chisel._
|
||||
import freechips.rocketchip.tilelink._
|
||||
import freechips.rocketchip.util._
|
||||
|
||||
class SourceB(info: ChipLinkInfo) extends Module
|
||||
{
|
||||
val io = new Bundle {
|
||||
val b = Decoupled(new TLBundleB(info.edgeIn.bundle))
|
||||
val q = Decoupled(UInt(width = info.params.dataBits)).flip
|
||||
}
|
||||
|
||||
// Find the optional cache (at most one)
|
||||
val cache = info.edgeIn.client.clients.filter(_.supportsProbe).headOption
|
||||
|
||||
// A simple FSM to generate the packet components
|
||||
val state = RegInit(UInt(0, width = 2))
|
||||
val s_header = UInt(0, width = 2)
|
||||
val s_address0 = UInt(1, width = 2)
|
||||
val s_address1 = UInt(2, width = 2)
|
||||
val s_data = UInt(3, width = 2)
|
||||
|
||||
private def hold(key: UInt)(data: UInt) = {
|
||||
val enable = state === key
|
||||
Mux(enable, data, RegEnable(data, enable))
|
||||
}
|
||||
|
||||
// Extract header fields
|
||||
val Seq(_, q_opcode, q_param, q_size, _, _) =
|
||||
info.decode(io.q.bits).map(hold(s_header) _)
|
||||
|
||||
// Latch address
|
||||
val q_address0 = hold(s_address0)(io.q.bits)
|
||||
val q_address1 = hold(s_address1)(io.q.bits)
|
||||
|
||||
val (_, q_last) = info.firstlast(io.q, Some(UInt(1)))
|
||||
val q_hasData = !q_opcode(2)
|
||||
val b_first = RegEnable(state =/= s_data, io.q.fire())
|
||||
|
||||
when (io.q.fire()) {
|
||||
switch (state) {
|
||||
is (s_header) { state := s_address0 }
|
||||
is (s_address0) { state := s_address1 }
|
||||
is (s_address1) { state := Mux(q_hasData, s_data, s_header) }
|
||||
is (s_data) { state := Mux(!q_last, s_data, s_header) }
|
||||
}
|
||||
}
|
||||
|
||||
// Feed our preliminary B channel via the Partial Extractor FSM
|
||||
val extract = Module(new ParitalExtractor(io.b.bits))
|
||||
io.b <> extract.io.o
|
||||
val b = extract.io.i
|
||||
extract.io.last := q_last
|
||||
|
||||
b.bits.opcode := q_opcode
|
||||
b.bits.param := q_param
|
||||
b.bits.size := q_size
|
||||
b.bits.source := UInt(cache.map(_.sourceId.start).getOrElse(0))
|
||||
b.bits.address := Cat(q_address1, q_address0)
|
||||
b.bits.mask := MaskGen(q_address0, q_size, info.params.dataBytes)
|
||||
b.bits.data := io.q.bits
|
||||
|
||||
val xmit = q_last || state === s_data
|
||||
b.valid := io.q.valid && xmit
|
||||
io.q.ready := b.ready || !xmit
|
||||
}
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
// See LICENSE for license details.
|
||||
package sifive.blocks.devices.chiplink
|
||||
|
||||
import Chisel._
|
||||
import freechips.rocketchip.tilelink._
|
||||
import freechips.rocketchip.util._
|
||||
|
||||
class SourceC(info: ChipLinkInfo) extends Module
|
||||
{
|
||||
val io = new Bundle {
|
||||
val c = Decoupled(new TLBundleC(info.edgeOut.bundle))
|
||||
val q = Decoupled(UInt(width = info.params.dataBits)).flip
|
||||
// Used by D to find the txn
|
||||
val d_tlSource = Valid(UInt(width = info.params.sourceBits)).flip
|
||||
val d_clSource = UInt(OUTPUT, width = info.params.clSourceBits)
|
||||
}
|
||||
|
||||
// CAM of sources used for release
|
||||
val cam = Module(new CAM(info.params.sourcesPerDomain, info.params.clSourceBits))
|
||||
|
||||
// A simple FSM to generate the packet components
|
||||
val state = RegInit(UInt(0, width = 2))
|
||||
val s_header = UInt(0, width = 2)
|
||||
val s_address0 = UInt(1, width = 2)
|
||||
val s_address1 = UInt(2, width = 2)
|
||||
val s_data = UInt(3, width = 2)
|
||||
|
||||
private def hold(key: UInt)(data: UInt) = {
|
||||
val enable = state === key
|
||||
Mux(enable, data, RegEnable(data, enable))
|
||||
}
|
||||
|
||||
// Extract header fields
|
||||
val Seq(_, q_opcode, q_param, q_size, _, q_source) =
|
||||
info.decode(io.q.bits).map(hold(s_header) _)
|
||||
|
||||
// Latch address
|
||||
val q_address0 = hold(s_address0)(io.q.bits)
|
||||
val q_address1 = hold(s_address1)(io.q.bits)
|
||||
|
||||
val (_, q_last) = info.firstlast(io.q, Some(UInt(2)))
|
||||
val q_hasData = q_opcode(0)
|
||||
val c_first = RegEnable(state =/= s_data, io.q.fire())
|
||||
|
||||
when (io.q.fire()) {
|
||||
switch (state) {
|
||||
is (s_header) { state := s_address0 }
|
||||
is (s_address0) { state := s_address1 }
|
||||
is (s_address1) { state := Mux(q_hasData, s_data, s_header) }
|
||||
is (s_data) { state := Mux(!q_last, s_data, s_header) }
|
||||
}
|
||||
}
|
||||
|
||||
// Determine if the request is legal. If not, route to error device.
|
||||
val q_address = Cat(q_address1, q_address0)
|
||||
val exists = info.edgeOut.manager.containsSafe(q_address)
|
||||
private def writeable(m: TLManagerParameters): Boolean = if (m.supportsAcquireB) m.supportsAcquireT else m.supportsPutFull
|
||||
private def acquireable(m: TLManagerParameters): Boolean = m.supportsAcquireB || m.supportsAcquireT
|
||||
private def toBool(x: Boolean) = Bool(x)
|
||||
val writeOk = info.edgeOut.manager.fastProperty(q_address, writeable, toBool)
|
||||
val acquireOk = info.edgeOut.manager.fastProperty(q_address, acquireable, toBool)
|
||||
val q_legal = exists && (!q_hasData || writeOk) && acquireOk
|
||||
|
||||
// Look for an available source in the correct domain
|
||||
val q_release = q_opcode === TLMessages.Release || q_opcode === TLMessages.ReleaseData
|
||||
val source_ok = !q_release || cam.io.alloc.ready
|
||||
val source = cam.io.key holdUnless c_first
|
||||
|
||||
io.c.bits.opcode := q_opcode
|
||||
io.c.bits.param := q_param
|
||||
io.c.bits.size := q_size
|
||||
io.c.bits.source := Mux(q_release, source, UInt(0)) // always domain 0
|
||||
io.c.bits.address := info.makeError(q_legal, q_address)
|
||||
io.c.bits.data := io.q.bits
|
||||
io.c.bits.error := Bool(false) // !!! need a packet footer
|
||||
|
||||
val stall = c_first && !source_ok
|
||||
val xmit = q_last || state === s_data
|
||||
io.c.valid := (io.q.valid && !stall) && xmit
|
||||
io.q.ready := (io.c.ready && !stall) || !xmit
|
||||
cam.io.alloc.valid := q_release && c_first && xmit && io.q.valid && io.c.ready
|
||||
cam.io.alloc.bits := q_source
|
||||
|
||||
// Free the CAM entries
|
||||
io.d_clSource := cam.io.data
|
||||
cam.io.free := io.d_tlSource
|
||||
}
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
// See LICENSE for license details.
|
||||
package sifive.blocks.devices.chiplink
|
||||
|
||||
import Chisel._
|
||||
import freechips.rocketchip.tilelink._
|
||||
import freechips.rocketchip.util._
|
||||
|
||||
class SourceD(info: ChipLinkInfo) extends Module
|
||||
{
|
||||
val io = new Bundle {
|
||||
val d = Decoupled(new TLBundleD(info.edgeIn.bundle))
|
||||
val q = Decoupled(UInt(width = info.params.dataBits)).flip
|
||||
// Used by E to find the txn
|
||||
val e_tlSink = Valid(UInt(width = info.params.sinkBits)).flip
|
||||
val e_clSink = UInt(OUTPUT, width = info.params.clSinkBits)
|
||||
}
|
||||
|
||||
// We need a sink id CAM
|
||||
val cam = Module(new CAM(info.params.sinks, info.params.clSinkBits))
|
||||
|
||||
// Map ChipLink transaction to TileLink source
|
||||
val cl2tl = info.sourceMap.map(_.swap)
|
||||
val nestedMap = cl2tl.groupBy(_._1.domain).mapValues(_.map { case (TXN(_, cls), tls) => (cls, tls) })
|
||||
val muxes = Seq.tabulate(info.params.domains) { i =>
|
||||
info.mux(nestedMap.lift(i).getOrElse(Map(0 -> 0)))
|
||||
}
|
||||
|
||||
// The FSM states
|
||||
val state = RegInit(UInt(0, width = 2))
|
||||
val s_header = UInt(0, width = 2)
|
||||
val s_sink = UInt(1, width = 2)
|
||||
val s_data = UInt(2, width = 2)
|
||||
|
||||
private def hold(key: UInt)(data: UInt) = {
|
||||
val enable = state === key
|
||||
Mux(enable, data, RegEnable(data, enable))
|
||||
}
|
||||
|
||||
// Extract header fields from the message
|
||||
val Seq(_, q_opcode, q_param, q_size, q_domain, q_source) =
|
||||
info.decode(io.q.bits).map(hold(s_header) _)
|
||||
|
||||
// Extract sink from the optional second beat
|
||||
val q_sink = hold(s_sink)(io.q.bits(15, 0))
|
||||
|
||||
val q_grant = q_opcode === TLMessages.Grant || q_opcode === TLMessages.GrantData
|
||||
val (_, q_last) = info.firstlast(io.q, Some(UInt(3)))
|
||||
val d_first = RegEnable(state =/= s_data, io.q.fire())
|
||||
val s_maybe_data = Mux(q_last, s_header, s_data)
|
||||
|
||||
when (io.q.fire()) {
|
||||
switch (state) {
|
||||
is (s_header) { state := Mux(q_grant, s_sink, s_maybe_data) }
|
||||
is (s_sink) { state := s_maybe_data }
|
||||
is (s_data) { state := s_maybe_data }
|
||||
}
|
||||
}
|
||||
|
||||
// Look for an available sink
|
||||
val sink_ok = !q_grant || cam.io.alloc.ready
|
||||
val sink = cam.io.key holdUnless d_first
|
||||
val stall = d_first && !sink_ok
|
||||
val xmit = q_last || state === s_data
|
||||
|
||||
io.d.bits.opcode := q_opcode
|
||||
io.d.bits.param := q_param
|
||||
io.d.bits.size := q_size
|
||||
io.d.bits.source := Vec(muxes.map { m => m(q_source) })(q_domain)
|
||||
io.d.bits.sink := Mux(q_grant, sink, UInt(0))
|
||||
io.d.bits.data := io.q.bits
|
||||
io.d.bits.error := Bool(false) // !!! frack => need packet footer?
|
||||
|
||||
io.d.valid := (io.q.valid && !stall) && xmit
|
||||
io.q.ready := (io.d.ready && !stall) || !xmit
|
||||
|
||||
cam.io.alloc.valid := q_grant && d_first && xmit && io.q.valid && io.d.ready
|
||||
cam.io.alloc.bits := q_sink
|
||||
|
||||
// Free the CAM
|
||||
io.e_clSink := cam.io.data
|
||||
cam.io.free := io.e_tlSink
|
||||
}
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
// See LICENSE for license details.
|
||||
package sifive.blocks.devices.chiplink
|
||||
|
||||
import Chisel._
|
||||
import freechips.rocketchip.tilelink._
|
||||
import freechips.rocketchip.util._
|
||||
|
||||
class SourceE(info: ChipLinkInfo) extends Module
|
||||
{
|
||||
val io = new Bundle {
|
||||
val e = Decoupled(new TLBundleE(info.edgeOut.bundle))
|
||||
val q = Decoupled(UInt(width = info.params.dataBits)).flip
|
||||
}
|
||||
|
||||
// Extract header fields
|
||||
val Seq(_, _, _, _, _, q_sink) = info.decode(io.q.bits)
|
||||
|
||||
io.q.ready := io.e.ready
|
||||
io.e.valid := io.q.valid
|
||||
io.e.bits.sink := q_sink
|
||||
}
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
// See LICENSE for license details.
|
||||
package sifive.blocks.devices.chiplink
|
||||
|
||||
import Chisel._
|
||||
import freechips.rocketchip.tilelink._
|
||||
import freechips.rocketchip.util._
|
||||
|
||||
class TX(info: ChipLinkInfo) extends Module
|
||||
{
|
||||
val io = new Bundle {
|
||||
val c2b_send = Bool(OUTPUT)
|
||||
val c2b_data = UInt(OUTPUT, info.params.dataBits)
|
||||
val a = new AsyncBundle(info.params.crossingDepth, new DataLayer(info.params)).flip
|
||||
val b = new AsyncBundle(info.params.crossingDepth, new DataLayer(info.params)).flip
|
||||
val c = new AsyncBundle(info.params.crossingDepth, new DataLayer(info.params)).flip
|
||||
val d = new AsyncBundle(info.params.crossingDepth, new DataLayer(info.params)).flip
|
||||
val e = new AsyncBundle(info.params.crossingDepth, new DataLayer(info.params)).flip
|
||||
val sa = DecoupledIO(new DataLayer(info.params)).flip
|
||||
val sb = DecoupledIO(new DataLayer(info.params)).flip
|
||||
val sc = DecoupledIO(new DataLayer(info.params)).flip
|
||||
val sd = DecoupledIO(new DataLayer(info.params)).flip
|
||||
val se = DecoupledIO(new DataLayer(info.params)).flip
|
||||
val rxc = new AsyncBundle(1, new CreditBump(info.params)).flip
|
||||
val txc = new AsyncBundle(1, new CreditBump(info.params)).flip
|
||||
}
|
||||
|
||||
// Currently available credits
|
||||
val rx = RegInit(CreditBump(info.params, 0))
|
||||
val tx = RegInit(CreditBump(info.params, 0))
|
||||
val first = RegInit(Bool(true))
|
||||
|
||||
// Constantly pull credits from RX
|
||||
val rxInc = FromAsyncBundle(io.rxc)
|
||||
val txInc = FromAsyncBundle(io.txc)
|
||||
rxInc.ready := Bool(true)
|
||||
txInc.ready := Bool(true)
|
||||
|
||||
// Cross the requests (if necessary)
|
||||
val sync = info.params.syncTX
|
||||
val a = if (sync) ShiftQueue(io.sa, 2) else FromAsyncBundle(io.a)
|
||||
val b = if (sync) ShiftQueue(io.sb, 2) else FromAsyncBundle(io.b)
|
||||
val c = if (sync) ShiftQueue(io.sc, 2) else FromAsyncBundle(io.c)
|
||||
val d = if (sync) ShiftQueue(io.sd, 2) else FromAsyncBundle(io.d)
|
||||
val e = if (sync) ShiftQueue(io.se, 2) else FromAsyncBundle(io.e)
|
||||
|
||||
private def ioX = Seq(a, b, c, d, e)
|
||||
val validABCDE = Cat(ioX.map(_.valid).reverse)
|
||||
|
||||
// Calculate if the packet will fit
|
||||
val txDec = CreditBump(info.params, 0)
|
||||
val spaceABCDE = Cat(((tx.X zip txDec.X) zip ioX) .map { case ((credit, reduce), beat) =>
|
||||
val delta = credit -& beat.bits.beats
|
||||
reduce := Mux(beat.fire() && first, delta, credit)
|
||||
delta.asSInt >= SInt(0)
|
||||
}.reverse)
|
||||
val requestABCDE = validABCDE & spaceABCDE
|
||||
|
||||
// How often should we force transmission of a credit update? sqrt
|
||||
val xmitBits = log2Ceil(info.params.Qdepth) / 2
|
||||
val xmit = RegInit(UInt(0, width = xmitBits))
|
||||
val forceXmit = xmit === UInt(0)
|
||||
|
||||
// Frame an update of the RX credits
|
||||
val (header, rxLeft) = rx.toHeader
|
||||
val f = Wire(Decoupled(new DataLayer(info.params)))
|
||||
f.valid := requestABCDE === UInt(0) || forceXmit
|
||||
f.bits.data := header
|
||||
f.bits.last := Bool(true)
|
||||
f.bits.beats := UInt(1)
|
||||
|
||||
when (!forceXmit) { xmit := xmit - UInt(1) }
|
||||
when (f.fire()) { xmit := ~UInt(0, width = xmitBits) }
|
||||
|
||||
// Include the F credit channel in arbitration
|
||||
val ioF = ioX :+ f
|
||||
val space = Cat(UInt(1), spaceABCDE)
|
||||
val request = Cat(f.valid, requestABCDE)
|
||||
val valid = Cat(f.valid, validABCDE)
|
||||
|
||||
// Select a channel to transmit from those with data and space
|
||||
val lasts = Cat(ioF.map(_.bits.last).reverse)
|
||||
val readys = TLArbiter.roundRobin(6, request, first)
|
||||
val winner = readys & request
|
||||
val state = RegInit(UInt(0, width=6))
|
||||
val grant = Mux(first, winner, state)
|
||||
val allowed = Mux(first, readys & space, state)
|
||||
(ioF zip allowed.toBools) foreach { case (beat, sel) => beat.ready := sel }
|
||||
|
||||
state := grant
|
||||
first := (grant & lasts).orR
|
||||
|
||||
// Form the output beat
|
||||
io.c2b_send := RegNext(RegNext(first || (state & valid) =/= UInt(0), Bool(false)), Bool(false))
|
||||
io.c2b_data := RegNext(Mux1H(RegNext(grant), RegNext(Vec(ioF.map(_.bits.data)))))
|
||||
|
||||
// Update the credit trackers
|
||||
rx := Mux(f.fire(), rxLeft, rx) + Mux(rxInc.fire(), rxInc.bits, CreditBump(info.params, 0))
|
||||
tx := txDec + Mux(txInc.fire(), txInc.bits, CreditBump(info.params, 0))
|
||||
}
|
||||
Loading…
Reference in New Issue