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riscv/sifive-blocks
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106 Commits 1 Branch 0 Tags
1feaefe4c5c8e36682f29508b8e5e2ee9c4d7038
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Megan Wachs 1feaefe4c5 i2c, uart: Use Synchronizer primitives for the inputs
2017-09-05 18:32:37 -07:00
src/main/scala
i2c, uart: Use Synchronizer primitives for the inputs
2017-09-05 18:32:37 -07:00
vsrc
Updates to go with the fpga-shells directory
2017-08-17 18:12:49 -07:00
.gitignore
Add /target to .gitignore.
2016-11-30 13:29:54 -08:00
LICENSE
Initial commit.
2016-11-29 04:08:44 -08:00
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Description
Freedom RTL blocks (https://github.com/sifive/sifive-blocks)
280 KiB
0 Stars 1 Watchers 0 Forks
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Scala 99.8%
Verilog 0.2%
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