riscv/sifive-blocks
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Freedom RTL blocks (https://github.com/sifive/sifive-blocks)
102 Commits 1 Branch 0 Tags 280 KiB
Scala 99.8%
Verilog 0.2%
402017d34e
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Megan Wachs 402017d34e Merge pull request #35 from sifive/spi-buffers 
spi: put a request buffer infront of SPI
2017-08-20 16:47:01 -07:00
src/main/scala spi: Make memory mapped interface depth a parameter 2017-08-20 12:39:38 -07:00
vsrc Updates to go with the fpga-shells directory 2017-08-17 18:12:49 -07:00
.gitignore Add /target to .gitignore. 2016-11-30 13:29:54 -08:00
LICENSE Initial commit. 2016-11-29 04:08:44 -08:00