riscv/sifive-blocks
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Do not allow status read if status.transferInProgress is going to change next cycle

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This commit is contained in:
Alex Solomatnikov 2018-02-22 18:43:39 -08:00
parent 6c5b80671c
commit ef8139f18c
1 changed files with 5 additions and 2 deletions
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7
src/main/scala/devices/i2c/I2C.scala
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@ -514,11 +514,14 @@ trait HasI2CModuleContents extends MultiIOModule with HasRegMap {
status.arbLost := false.B
}
status.transferInProgress := cmd.read || cmd.write
status.irqFlag := (cmdAck || arbLost || status.irqFlag) && !cmd.irqAck
status.irqFlag := (cmdAck || arbLost || status.irqFlag) && !cmd.irqAck // interrupt request flag is always generated
val statusReadReady = Reg(init = true.B)
when (!statusReadReady) {
when (cmdAck || arbLost) { // => cmd.read or cmd.write deassert 1 cycle later => transferInProgress deassert 2 cycles later
statusReadReady := false.B // do not allow status read if status.transferInProgress is going to change
}
.elsewhen (!statusReadReady) {
statusReadReady := true.B
}