Wesley W. Terpstra
3e7bdcbf5e
tilelink2: Fragmenter should ignore error when not valid
2017-05-09 17:35:26 -07:00
Wesley W. Terpstra
43c9f5fe7e
tilelink2: keep earlyAck Fragmenter sources distinct
2017-05-09 17:35:22 -07:00
Andrew Waterman
3a9bbd7e58
Merge branch 'master' into vectored-stvec
2017-05-08 14:08:09 -07:00
Wesley W. Terpstra
2d8a49cc06
tilelink2: Fragmenter client must request global FIFO
2017-05-08 00:56:45 -07:00
Wesley W. Terpstra
36f4584bb1
axi4: Test AXI4-Lite in regression
2017-05-08 00:31:35 -07:00
Wesley W. Terpstra
3209e58845
axi4: SRAM support 0 userBits
2017-05-08 00:31:14 -07:00
Wesley W. Terpstra
db76ff2d86
axi4: Deinterleaver must gather R also for single ID
...
In order to guarantee that a complete R can be sent without
sinking B, the Deinterleaver must do its job even on AXI-Lite.
2017-05-08 00:17:06 -07:00
Wesley W. Terpstra
8fc27b0bf2
axi4: IdIndexer; a single ID does NOT imply no response interleaving
...
Some slaves may never send R until you process their B.
Thus, while there is no read response interleaving, there
is still interleaving between R and B, which breaks AXI4ToTL.
2017-05-08 00:17:06 -07:00
Wesley W. Terpstra
4847c32599
tilelink: ToAXI4 - must interlock till last beat
...
AXI4 makes no guarantee that bursts are handled atomicly.
Thus, you could be part-way through a read burst and suddenly
a write cuts ahead and is visible later, violating FIFO.
2017-05-08 00:17:06 -07:00
Wesley W. Terpstra
8169ba6411
axi4: IdIndexer now handles 0-width IDs
2017-05-08 00:17:02 -07:00
Andrew Waterman
7eefc12705
Support vectored stvec interrupts, too
...
137812654e
2017-05-07 15:40:08 -07:00
Andrew Waterman
c6135a02df
Revert "rocket: hard-wire UXL/SXL fields to 0"
...
This reverts commit ea0714bfcb
.
We've waffled on this matter in the priv spec: 326bec83de
2017-05-07 15:23:21 -07:00
Andrew Waterman
dd1546fd69
Check PPN LSBs for superpage PTEs
...
5a32fe8782
2017-05-05 15:30:09 -07:00
Scott Johnson
1b3b228790
ITIM supports PutPartial
2017-05-04 00:57:52 -07:00
Andrew Waterman
398600d4da
Interlock to prevent ITIM hazard when tl.a.valid & tl.d.valid & !tl.d.ready
2017-05-04 00:57:29 -07:00
Scott Johnson
1cc665717d
Wes fix for AXI2TL timeout when writes backed up
2017-05-04 00:54:21 -07:00
Andrew Waterman
fa6ecdf813
Fix RVC/uncacheable instruction memory performance bug
...
9c1d126965
was an incomplete fix, so
sometimes we were requesting pipeline replays when they weren't
necessary.
2017-05-03 17:52:06 -07:00
Henry Cook
1f1240baf1
fuzzer: allow fuzzing range to be overridden
2017-05-03 15:29:14 -07:00
Megan Wachs
f8c92d2669
Merge branch 'master' into pipeline-mmio
2017-05-03 08:37:12 -07:00
Andrew Waterman
4efcb5a139
Increase frontend decoupling ( #722 )
...
Reduce pathological RVC stalls
2017-05-03 07:54:46 -07:00
Henry Cook
05ca88fb47
Merge branch 'master' into pipeline-mmio
2017-05-03 01:59:59 -07:00
Megan Wachs
922a8ef5e0
local_interrupts: Correct off-by-1 if there is no SEIP
2017-05-02 21:55:25 -07:00
Henry Cook
4dd3345db2
Merge branch 'master' into pipeline-mmio
2017-05-02 16:23:26 -07:00
Andrew Waterman
3a1a37d41b
Support PutPartial in ScratchpadSlavePort
2017-05-02 03:07:02 -07:00
Andrew Waterman
938b089543
Remove legacy devices that use AMOALU
...
I'm going to change the AMOALU API, and so I'm removing dependent dead code.
2017-05-02 03:05:41 -07:00
Andrew Waterman
f8151ce786
Remove subword load muxing in ScratchpadSlavePort
2017-05-02 00:14:46 -07:00
Andrew Waterman
044b6ed3f9
Improve logical ops in AMOALU
...
As with integer ALU, shave off some muxing.
2017-05-02 00:14:46 -07:00
Andrew Waterman
f49172b5bc
ScratchpadSlavePort doesn't support byte/halfword atomics
2017-05-02 00:14:46 -07:00
Wesley W. Terpstra
fe280187a1
axi4: Fragmenter cuts all input channel readys
...
AXI4 forbids any input to lead combinationally to an output.For the AXI4ToTL
direction, front-load the cuts for {AW, AR, W}.readyAXI4ToTL makes the R and
B channels irrevocable.
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
3d06f01a2c
rocket: turn on early ack for ITIM
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
58a4529cc5
axi4: the last missing piece for safe FIFO ordering
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
b0b5601e8d
axi4: ToTL correct error handling
...
If there is an illegal AWADDR = 0x2 on a 32-bit bus, remapping it
to an aligned address on the error device may make the mask
inconsistent with the address + size.
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
661015a78d
axi4: switch arbiter to round robin
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
976af7a8c7
tilelink2: better width inference for {left,right}OR
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
40f18e6e43
diplomacy: optimize IdRange overlap detection
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
30f1f1e7c7
rocket: turn on early ack for DTIM
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
6ee69454c3
tilelink2: Fragmenter now supports early Ack
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
e09fa866b7
tilelink2: FIFOFixer should NOT change client request status
...
Just because some clients are not FIFO does not matter. Downstream
FIFOFixers will still present a legitimate single domain to those
client who care.
2017-05-01 22:53:41 -07:00
Scott Johnson
b040a462c9
Wes's change to remove user bits from external AXI interface, and add 1 cycle latency to make sure external AXI is compliant
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
a71f708dc7
rocketchip: move the Error device to 0x3000
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
d27e1928dd
axi4: make maxFlight a per-master parameter
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
e1a072a644
axi4: massage test cases into shape again
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
9f08c484bd
tilelink2: ToAXI4 provide FIFO order semantics
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
61a6f94196
axi4: get unit tests legal again
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
bf5cb396b9
rocketchip: relax mmio no-interleaving requirement
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
24f577c156
axi4: Deinterleaver ensures R channel ID does not change till last
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
b4188ee625
axi4: ToTL supporting pipelined MMIO
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
ca2cb033cd
rocketchip: fix uses of AXI4 Fragmenter
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
e100a943ea
axi4: simplify Fragmenter by using user bits
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
7a1d107c9e
rocketchip: include an ErrorSlave by default
2017-05-01 22:53:37 -07:00
Wesley W. Terpstra
641a4d577a
tilelink2: Error device for returning errors on demand
2017-05-01 22:53:02 -07:00
Wesley W. Terpstra
a580b17ece
axi4: IdIndexer => reduce number of needed ids
2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
06efc01d96
axi4: an adapter to remove user bits
2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
f1217519f1
axi4: RegisterRouter; concurrent response illegal in AXI
2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
5163ccd11f
axi4: RegisterRouter supports user bits
2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
de6ea9b442
axi4: support user bits in SRAM
2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
396ecacda4
AXI4: add an optional user bundle field
2017-05-01 22:53:01 -07:00
Andrew Waterman
d6e69066a5
Fix ITIM loads ( #716 )
...
An incorrectly-set ready signal caused bad data to be read from the RAM.
2017-05-01 17:41:25 -07:00
Andrew Waterman
dd85d7e0a0
I$: Don't raise io.resp.valid if io.s1_kill was high previous cycle
...
@solomatnikov found the bug. It doesn't manifest in Rocket because the
Frontend masks io.resp.valid with s2_valid.
2017-04-28 16:44:58 -07:00
Megan Wachs
d67738204f
Interrupts: Less Pessimistic Synchronization ( #714 )
...
* interrupts: Less pessimistic synchronization for the different interrupt types. There are some issues with the interrupt number assignments.
* interrupts: Allow an option to NOT synchronize all the external interrupts coming into PLIC
* interrupts: ExampleRocketChipTop uses PeripheryAsyncExtInterrupts. Realized 'abstract' doesn't do what I thought in Scala.
* interrupts: use consistent async/periph/core ordering
* interrupts: Properly condition on 0 External interrupts
* interrupts: CLINT is also synchronous to periph clock
2017-04-28 14:49:24 -07:00
Andrew Waterman
7416f2a17e
Unbreak groundtest
2017-04-28 02:10:33 -07:00
Andrew Waterman
8fd5ecdff8
Set io.cpu.resp.bits.addr for MMIO loads without affecting QoR
2017-04-27 19:50:38 -07:00
Andrew Waterman
7c70aa593e
Minor stylistic and QoR improvements to PLIC
2017-04-27 19:35:20 -07:00
Henry Cook
3d0ed80ef6
new parameters ResetVectorBits, MaxHartIdBits, and MaxPriorityLevels
2017-04-27 18:17:31 -07:00
Henry Cook
bdb526a9f0
coreplex: DefaultCoreplex => RocketPlex
2017-04-27 18:17:09 -07:00
Andrew Waterman
99de42d34c
Swap order of ITIM WidthWidget and Fragmenter
...
e99fa057ac
accidentally reversed them
2017-04-27 15:30:02 -07:00
Andrew Waterman
8c10caeef9
Express PMP mask generation with incrementer, not adder
...
DC apparently doesn't always pick up the ((x + 1) ^ x) idiom.
Use (x + ~(x + 1)) instead.
2017-04-27 15:16:29 -07:00
Henry Cook
e99fa057ac
cleanup scratchpad nodes
2017-04-27 14:02:05 -07:00
Andrew Waterman
b2b4725522
Fix zero-width wire issues when ITIM is disabled
2017-04-26 22:43:00 -07:00
Andrew Waterman
e23ee274f6
Size hartid field with NTiles, not XLen
2017-04-26 20:11:43 -07:00
Andrew Waterman
dc753bfa95
Fix I$ elaboration when ITIM is disabled
2017-04-26 19:35:35 -07:00
Andrew Waterman
80d826b94a
Make DTIM deduplicatable
2017-04-26 19:35:35 -07:00
Andrew Waterman
418879a47f
Add Instruction Tightly Integrated Memory
2017-04-26 19:35:35 -07:00
Andrew Waterman
ee6702e5e0
Support indexing 1-entry Seqs
...
It's a zero-width wire special case.
Closes #706 .
2017-04-26 19:35:35 -07:00
Andrew Waterman
2e23d46631
Use val instead of def in ECC calculations
...
This allows nicer-looking code to avoid generating lots of redundant nodes.
2017-04-26 19:35:35 -07:00
Megan Wachs
7ad4cc36f7
debug: Prevent writes to DATA/PROGBUF when busy
2017-04-26 11:11:21 -07:00
Henry Cook
7f5f1c7631
Merge branch 'master' into async_queue_option
2017-04-25 14:58:11 -07:00
Henry Cook
9bb0d92381
Merge branch 'master' into async_queue_option
2017-04-25 11:23:22 -07:00
Henry Cook
60d71efa36
ahb: make hreadyout fuzzing a sram parameter
2017-04-25 11:11:31 -07:00
Henry Cook
ca435c2f40
uncore: more verbose requires
2017-04-25 11:11:31 -07:00
Wesley W. Terpstra
f3ab23d068
dcache: fix stupidly wrong crossing comparison ( #703 )
2017-04-25 09:18:41 -07:00
Wesley W. Terpstra
4807ce7ced
dcache: put a flow Q to absorb back-pressure without restarting pipeline ( #701 )
...
* dcache: put a flow Q to absorb back-pressure without restarting pipeline
When used with a RationalCrossing, pipelined MMIO does not come out cleanly.
The first beat works, but if the second beat gets stalled, the pipeline is
restarted. This is a quick hacky test to absorb the beats. Perhaps a better
fix can be made to achieve the same effect.
* dcache: provision as few stages as possible
2017-04-24 23:28:04 -07:00
Wesley W. Terpstra
9c1d126965
Allow speculative fetch to uncacheable memory if it hits in I$ ( #700 )
...
@aswaterman it's in
2017-04-24 19:12:37 -07:00
Wesley W. Terpstra
11ff4dfbb9
rocket: seip (int 9) is only present if VM is enabled ( #699 )
2017-04-24 15:58:33 -07:00
Wesley W. Terpstra
d0f3004097
tilelink2: help tools save some registers in the WidthWidget ( #691 )
2017-04-24 15:13:58 -07:00
Andrew Waterman
65928dc6a0
Don't push RAS for "auipc ra, X; jalr ra, ra, Y"
2017-04-24 02:01:15 -07:00
Andrew Waterman
36a7971975
Bypass scoreboard to reduce MMIO latency
2017-04-24 02:01:15 -07:00
Andrew Waterman
845e6f7458
Filter out duplicate test suites
...
I botched the refactoring in 5934c7b4b9
2017-04-24 02:01:15 -07:00
Andrew Waterman
f2d4cb8152
Update RAS speculatively from fetch stage
2017-04-24 02:01:15 -07:00
Andrew Waterman
3b2c15b648
Use tininess-after-rounding in FPU
2017-04-24 02:01:15 -07:00
Andrew Waterman
c36c171202
Use correct interrupt priority order
2017-04-24 02:01:15 -07:00
Andrew Waterman
bf861293d9
Add ShiftQueue; use it
2017-04-24 02:01:15 -07:00
Andrew Waterman
d24d8ff84b
Don't stall the frontend, making it easier to add more features later
2017-04-24 02:01:15 -07:00
Andrew Waterman
061a0adceb
Fetch smaller parcels from the I$
2017-04-24 02:01:15 -07:00
Ben Keller
0aa8f7d61d
Add narrowData option to AsyncQueue.
...
This option reduces the number of wires that cross the clock boundary.
This can be a useful feature if the clock boundary coincides with
a voltage boundary, in which case the number of level shifters is reduced.
However, this introduces a path that crosses from sink->source->sink domain,
so the option is disabled by default.
2017-04-21 16:31:17 -07:00
Megan Wachs
c72b15f2a0
Down with any require() statement that makes me RTFC
2017-04-21 15:44:42 -07:00
Henry Cook
54820e094d
Make more require statements in diplomacy verbose ( #693 )
...
* diplomacy: add more verbose requirements
* bump firrtl
2017-04-20 13:18:39 -07:00
Henry Cook
ef8a819763
Miscellaneous periphery improvements ( #689 )
...
* fifofixer: work around zero-width wires for single source id
* periphery: sourceshrinker takes maxInFlight parameter
2017-04-20 11:28:00 -07:00
Megan Wachs
9002e7e532
debug: Debug Module needs to handle DMI NOPs even if DTM won't send them.
2017-04-20 10:19:50 -07:00
Megan Wachs
cc7f0a5b7a
debug: whitespace cleanup
2017-04-20 10:19:50 -07:00
Megan Wachs
5934779082
debug: Clean up ValidReg assertion.
2017-04-20 10:19:50 -07:00
Megan Wachs
0c013a56c0
debug: Make DMI NOPs really NOPs.
...
This simplifies SW design and CDC issues.
2017-04-20 10:19:50 -07:00
Andrew Waterman
67404a665b
When not using a cache, LR/SC isn't legal even on cacheable memory
2017-04-20 08:47:03 -07:00
Megan Wachs
1be13d6b4c
PLIC: To avoid hazard between enable -> claim, enforce concurrency=1
2017-04-19 21:37:37 -07:00
Megan Wachs
3dfd584075
regmapper: remove the Pipe in the RegMapper Queue
...
With this pipe here, devices which declare concurrency > 0
actually accept transactions on the same cycle they complete
the previous one. This is unexpected behavior.
2017-04-19 21:37:37 -07:00
Wesley W. Terpstra
b4d17c76d1
coreplex: make rational+synchronous crossing configurable ( #688 )
2017-04-19 16:16:05 -07:00
Megan Wachs
408107447c
debug: DMI response should be busy, not zero, when there is an error. ( #685 )
2017-04-18 21:41:52 -07:00
Andrew Waterman
d82a0dc231
Mitigate D$ exception critical path, yet again
2017-04-18 00:47:58 -07:00
Andrew Waterman
c99ce7ce5d
Only report D$ exceptions on not-nacked accesses
2017-04-18 00:47:58 -07:00
Andrew Waterman
5934c7b4b9
Fix description of LR/SC test suites
2017-04-18 00:47:58 -07:00
Andrew Waterman
a956b78dd2
In TLBPermissions, merge across some region types
...
We only care whether they have side effects or not.
2017-04-18 00:47:58 -07:00
Andrew Waterman
6de6f38894
Pipeline D$ exception response into s2
2017-04-18 00:47:58 -07:00
Andrew Waterman
657f4d4e0c
Permit early grant acks to broadcast hub
2017-04-18 00:47:58 -07:00
Andrew Waterman
cc9ec1d51a
Send D$ grant acks early; accept release acks early
...
We now need to block the B-channel for a few cycles after a grant to
allow the processor to get at least one request through, preventing
livelock.
2017-04-18 00:47:58 -07:00
Andrew Waterman
728569c717
Reduce access-exception generation critical path
2017-04-18 00:47:58 -07:00
Andrew Waterman
a59a3f15e4
Disable LR/SC tests for scratchpad configs
2017-04-18 00:47:58 -07:00
Andrew Waterman
c366007a0d
Tighten PMAs for LR/SC and misaligned accesses
...
- LR/SC on cacheable memory only (not even scratchpad)
- No misaligned accesses on regions with get/put-effects
2017-04-18 00:47:58 -07:00
Andrew Waterman
74a7838de0
In TLBPermissions, don't merge regions of different types
2017-04-18 00:47:58 -07:00
Andrew Waterman
7871ec82c4
Guarantee probe forward progress during LR storm
2017-04-18 00:47:58 -07:00
Andrew Waterman
debcbca7de
Make PMP tolerant to PA size << VA size
2017-04-17 10:28:33 -07:00
Andrew Waterman
a454edaaf7
Treat exceptions as steps for the purposes of single-stepping
2017-04-17 10:28:33 -07:00
Megan Wachs
af6b2d8051
debug: DATA Region has to be aligned for ld/sd to correctly detect 64-bit cores.
2017-04-17 10:28:33 -07:00
Megan Wachs
b44d5f9386
debug: correctly consider .transfer bit in COMMAND
2017-04-17 10:28:33 -07:00
Megan Wachs
79477fbea6
debug: Properly consider 'transfer' bit
2017-04-17 10:28:33 -07:00
Megan Wachs
2dc4be6294
debug: remove preexec. Simplify the state machine since you can always just 'execute' once.
2017-04-17 10:28:33 -07:00
Wesley W. Terpstra
7b8af96fc2
diplomacy: use circles for nodes again
2017-04-14 18:09:14 -07:00
Wesley W. Terpstra
2f22fca615
rocket: reverse input edge for better output
2017-04-14 18:09:14 -07:00
Wesley W. Terpstra
ae8fd0c60f
graphML: don't draw unconnected LazyModules
2017-04-14 18:09:14 -07:00
Wesley W. Terpstra
fcf774f125
graphML: reverse interrupt arrows
2017-04-14 18:09:14 -07:00
Jacob Chang
d3925f0998
Add hooks to print debug information into the graphml file
2017-04-14 18:09:14 -07:00
Wesley W. Terpstra
ba8be17c9a
tilelink2: RAMModel, use CRC16 to check AMO response
2017-04-14 15:13:40 -07:00
Wesley W. Terpstra
6aeec673f2
util: add a CRC calculator
2017-04-14 15:13:40 -07:00
Wesley W. Terpstra
d794218ec3
tilelink2: RAMModel now checks atomic results
2017-04-14 15:13:40 -07:00
Wesley W. Terpstra
4f0ae1eab7
tilelink2: annotate which test generates RAMModel output
2017-04-14 15:13:40 -07:00
Wesley W. Terpstra
0b65fe9532
unittest: put AtomicAutomata under regression
2017-04-14 15:13:39 -07:00
Wesley W. Terpstra
248acbd1b4
tilelink2: add a generic TL2 atomic evaulation unit
2017-04-14 15:13:39 -07:00
Megan Wachs
fd7f4a4c0f
jtag: make it easier to assign MFR ID externally
2017-04-14 01:03:11 -07:00
Andrew Waterman
34d45b4fb0
Fix whitespace error
2017-04-14 01:03:11 -07:00
Andrew Waterman
fdfcffb0b2
Catch bad physical address MSBs when VA size > PA size
2017-04-14 01:03:11 -07:00
Andrew Waterman
6fbbccca3e
Improve Seq indexing QoR
2017-04-14 01:03:11 -07:00
Andrew Waterman
d203c4c654
Check AMO operation legality in TLB
2017-04-14 01:03:11 -07:00
Yunsup Lee
6359ff96e5
Several ScratchpadSlavePort bug fixes ( #676 )
...
* only replicate scratch slave d-channel resp when AMO req
* dtim: port can't support put partial mask with holes
* dtim: use \!isRead instead of isAMO
* Fix ScratchpadSlavePort looking at wrong Acquire message
Rename acq to a in the helper method.
Delete isRead and isWrite altogether.
2017-04-13 23:25:51 -07:00
Andrew Waterman
b9e042d2bf
Unconditionally write badaddr, possibly to zero
...
59d33f6b83
2017-04-12 13:35:02 -07:00
Jim Lawson
907d369bde
Remove tests obsoleted by new FP encoding proposal ( #672 )
2017-04-11 19:12:35 -07:00
Wesley W. Terpstra
1c36ab8bf7
Fragmenter: forbid multiple sink IDs
...
Otherwise a slave might respond with different IDs for different
requests and the Fragmenter would violate the requirement that
control signals remain unchanged for a burst.
2017-04-11 12:38:00 -07:00
Wesley W. Terpstra
84dc2ae822
CacheCork: remove probe support
2017-04-11 12:34:18 -07:00
Andrew Waterman
9a983c12a3
Implement new FP encoding proposal
...
https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/_r7hBlzsEd8/cWPyJKMzCQAJ
2017-04-10 22:38:25 -07:00
Andrew Waterman
470c6711a7
Do some CSE by hand, per @terpstra
2017-04-10 22:38:25 -07:00
Wesley W. Terpstra
71bf929505
maskgen: support wider granularity result ( #665 )
...
Sometimes it is useful to generate a mask with bits that correspond
to a larger unit than bytes.
2017-04-09 20:06:23 -07:00
Andrew Waterman
a43bf2feae
Add vectored interrupt support
...
4dcaa944ba
I also added a test, which does indeed pass, but I don't want to bump
riscv-tools for that alone:
ba6d88466a
2017-04-08 00:29:45 -07:00
Megan Wachs
051acee76c
Debug: Fix off-by-1 for detecting nonexistent harts.
2017-04-07 16:47:16 -07:00
Megan Wachs
01372e1686
use Wire() correctly to assign a value
2017-04-07 16:47:16 -07:00
Megan Wachs
9ae4838708
jtag: Get rid of chisel deprecation warnings
2017-04-07 16:47:16 -07:00
Megan Wachs
22c6f728c3
debug: Use flags for resume instead of program buffer. Untested.
2017-04-07 16:47:16 -07:00
Megan Wachs
d361e9e343
debug: temporarily leave preexec in place
2017-04-07 16:47:16 -07:00
Megan Wachs
0e2c34b0d6
debug: update register map with new spec
2017-04-07 16:47:16 -07:00
Megan Wachs
df5caba7bf
debug: Make it easier to override parts of the Default Debug Config ( #655 )
...
* Handle single-step with a pipeline stall, not a flush
The pipeline flush approach broke when I changed the pipeline stage
the flush happens from
* debug: Make it easier to override parts of the Default Debug Config
* Fix typo in Debug code generation
abstractGeneratedI should be abstractGeneratedS when pulling out the opcode.
This doesn't actually break anything, but fix it for clarity.
2017-04-06 10:33:17 -07:00
Andrew Waterman
c861c4925e
Don't signal access exceptions on invalid PTEs
...
The PPN should not be interpreted in this case.
2017-04-05 21:46:55 -07:00
Andrew Waterman
2e09253d26
Revive I$ parity option
...
Pipeline the parity check into the second stage, so that the data
RAM access + parity check do not become the critical path.
2017-04-05 21:46:55 -07:00
Andrew Waterman
43917dd59f
Get I$ s1_kill signal off the critical path
2017-04-05 21:46:55 -07:00
Andrew Waterman
744fb2e4b9
Cut imem.resp.ready critical path with a flow queue
...
This is only necessary for RVC, where the decode latency is much higher.
2017-04-05 21:46:55 -07:00
Andrew Waterman
3e72f9779f
Handle single-step with a pipeline stall, not a flush
...
The pipeline flush approach broke when I changed the pipeline stage
the flush happens from
2017-04-05 19:52:44 -07:00
Megan Wachs
2601740542
debug: fix some typos related to the ID->SEL mapping functions
2017-04-05 15:14:32 -07:00
Megan Wachs
b94f1f15b0
debug: redirect DMI NOPs to CONTROL register so things don't hang during reset
2017-04-05 15:14:32 -07:00
Megan Wachs
eef05cc1fc
debug: Enforce mapping between hartsel and hartid, use more reasonable defaults for DATA and PROGBUF sizes.
2017-04-05 15:14:32 -07:00
solomatnikov
127f121ef2
Preserve id_do_fence ( #651 )
2017-04-05 08:29:45 -07:00
Andrew Waterman
19f0ae64a0
Only set id_reg_fence when AMO/FENCE is actually executed
...
This is a performance bug, not a correctness bug. But randomly stalling
because of garbage bits coming out of the I$ should be avoided.
h/t @solomatnikov
2017-04-03 21:13:52 -07:00
Megan Wachs
629e9a2ef6
debug: Put DebugROM back inside the overall Debug Module ( #647 )
2017-04-03 16:36:53 -07:00
Megan Wachs
d2c1bdc2ce
Debug Controls ( #639 )
...
* debug: Bump OpenOCD version to one that drives resets and sets cmderr appropriately.
* debug: Export the dmactive and ndreset signals to the top level and drive reset as intended in the TestHarness.
2017-04-03 13:31:35 -07:00
Andrew Waterman
410e9cf736
I$ bugfix, to be reworked
2017-03-31 12:17:41 -07:00
Henry Cook
b9550e8523
Merge branch 'master' into name-rams
2017-03-30 17:36:01 -07:00
Andrew Waterman
a8a2ee711c
Give I$ RAMs consistent names
2017-03-30 15:50:54 -07:00
Andrew Waterman
2720095b8e
Give D$ RAMs consistent names
2017-03-30 15:49:14 -07:00
Andrew Waterman
70e7e90c02
Remove splitMetadata option from L1 caches
...
This is a property of the specific cache microarchitecture, not actually
an independently tunable knob.
2017-03-30 15:48:55 -07:00
Megan Wachs
9de06f8c83
Merge remote-tracking branch 'origin/master' into debug_v013_pr
2017-03-30 08:01:11 -07:00
Andrew Waterman
fd39eadcd6
New PMP encoding
2017-03-30 00:36:23 -07:00
Wesley W. Terpstra
2f2b472098
rocket: split the interrupt controller into its own node
2017-03-30 00:36:23 -07:00
Wesley W. Terpstra
a2fc51d65e
soc: compatible with "simple-bus" => scanned for platform devices
2017-03-30 00:36:23 -07:00
Andrew Waterman
3546c8d133
If any PMPs are supported, all CSRs exist
2017-03-30 00:36:23 -07:00
Andrew Waterman
8f73a58d90
Report access exception, not page fault, if page-table walk fails
2017-03-30 00:36:23 -07:00
Andrew Waterman
25232070ec
Don't redundantly set resp_ae in PTW
2017-03-30 00:36:23 -07:00
Andrew Waterman
80fb002962
Don't use Vec as lvalue
2017-03-30 00:36:23 -07:00
Henry Cook
d3bc99e253
get local interrupts out of the tile
2017-03-30 00:36:23 -07:00
solomatnikov
0b9fc94421
Assertion for back-to-back uncached and cached ops ( #631 )
2017-03-29 23:07:17 -07:00
Megan Wachs
d8033b20fc
Merge remote-tracking branch 'origin/master' into debug_v013_pr
2017-03-29 14:58:04 -07:00
Megan Wachs
375a039279
debug: Use proper write-1-to-clear ABSTRACTCS.cmderr behavior (because fesvr code is using correct spec)
2017-03-28 21:14:22 -07:00
Megan Wachs
ca9a5a1cf7
debug: Fixes in how the SimDTM was hooked up to FESVR
2017-03-28 21:13:45 -07:00
Andrew Waterman
8dfbf4532a
Use 1 MHz as default timebase ( #628 )
...
Defaulting to 0 prevents Linux from booting
2017-03-28 19:59:56 -07:00
Andrew Waterman
44fb3be7d0
Fix MMIO/cache refill concurrency bug in DCache
...
There's a structural hazard on s2_req, so disallow cache refill initiation
while any MMIO loads are in flight.
2017-03-28 17:16:29 -07:00
Andrew Waterman
db3ed12ce3
Fix regression in groundtest DummyPTW
...
Initialize all fields in PTWResp for determinism, which should
prevent this sort of problem in the future.
2017-03-28 00:56:14 -07:00
Andrew Waterman
4215f480ef
Write instruction to badaddr on illegal instruction traps
2017-03-28 00:56:14 -07:00
Megan Wachs
d6ab929c41
debug: Remove older version of JTAG interface as it is superseded by the one in jtag package.
2017-03-27 21:25:37 -07:00
Megan Wachs
bb64c92906
csr: Bring functionality in line with v13 spec. ebreak does not cause exception in Debug Mode, it just starts at Debug ROM again.
2017-03-27 21:21:48 -07:00
Megan Wachs
42ca597478
debug: Breaking change until FESVR is updated as well.
...
* Replace v11 Debug Module with v13 module.
* Correct all instantiating interfaces.
* Rename "Debug Bus" to "DMI" (Debug
Module Interface)
* Use Diplomacy interrupts for DebugInterrupt
* Seperate device for TLDebugROM
2017-03-27 21:19:08 -07:00
Megan Wachs
43804726ac
tilelink2: more helpful requirement message
2017-03-27 21:05:05 -07:00
Megan Wachs
0c3d85b52b
debug: add generated ROM contents and register fields.
2017-03-27 21:01:36 -07:00
Andrew Waterman
05cbdced78
Work around zero-entry vec issue in Chisel
2017-03-27 17:57:26 -07:00
Andrew Waterman
d42d8aaea7
Make SEIP writable
2017-03-27 16:37:09 -07:00
Andrew Waterman
c7c357e716
Add local interrupts to core (but not yet to coreplex)
2017-03-27 16:37:09 -07:00
Andrew Waterman
069858a20c
rocket: separate page faults from physical memory access exceptions
2017-03-27 16:37:09 -07:00
Andrew Waterman
ea0714bfcb
rocket: hard-wire UXL/SXL fields to 0
...
a2a3346e73
2017-03-27 16:37:09 -07:00
Wesley W. Terpstra
5b339b6bbd
tilelink2 Monitor: catch incorrect use of source ID
2017-03-27 16:30:46 -07:00
Wesley W. Terpstra
75eba294ec
DCache: Release from the correct ID as well
2017-03-27 16:30:46 -07:00
Wesley W. Terpstra
4959771c97
Revert "For D$, use source 0 through N-1 for MMIO, not 1 through N"
...
This reverts commit 0538dc77ce
.
2017-03-27 16:30:46 -07:00
Wesley W. Terpstra
fa7ead6357
Revert "Use Reg(Vec) instead of Seq(Reg) for DCache MMIO"
...
This reverts commit fb6498f2c3
.
2017-03-27 16:30:46 -07:00
Megan Wachs
70fa10fc55
Util: Add ResetCatchAndSync for synchronous deassert of Async Reset ( #615 )
2017-03-27 03:29:07 -07:00
Megan Wachs
08c4f7cea6
RocketTile: Create a wrapper for SyncRocketTile as well ( #616 )
...
* RocketTile: Create a wrapper for SyncRocketTile as well
There is no guarantee that debugInterrupt is synchronous
to tlClk, even though it is true in the current implementation.
It will not be true in future implementations, as decoupling
this allows the debugInterrupt to be asserted across tlClk
gating/reset scenarios.
Therefore, even for SyncRocketTile, the debug interrupt needs to be
synchronized to coreClk, and for RationalRocketTile, 1 cycle
of synchronization is not sufficient.
Even though other interrupts may be synchronized, we just
synchronize them all to simplify the code at the expense of
a few cycles latency.
It could still be nice to use a parameter vs hard coding "3".
* RocketTile: Actually use the SyncRocketTile wrapper to get properly synchronized resets.
2017-03-27 02:45:37 -07:00
Megan Wachs
11507ac7d6
TLROM: Use Resource as a parameter rather than assuming SimpleDevice.
...
This allows more flexibility e.g. considering the ROM as part of other
devices.
2017-03-26 20:58:14 -07:00
Megan Wachs
bf648514e3
TLROM: allow name and compatibility strings to be provided by subclasses.
2017-03-26 20:58:14 -07:00
Megan Wachs
8e6beb80be
Add ucb-art/chisel-jtag ( #612 )
...
* jtag: Add ucb-art/chisel-jtag to junctions.
* jtag: Add missing Utils file for Tristate and NegativeEdgeLatch
* jtag: move to a top-level package
2017-03-26 18:03:21 -07:00
Andrew Waterman
0e2b780089
Bump hardfloat, giving us the 5th rounding mode finally!
2017-03-26 14:20:16 -07:00
Andrew Waterman
e710e32f10
Implement new FP encoding proposal
...
Single-precision values are stored in the regfile as double-precision,
so that FSD on a single-precision value stores a proper double and
FLD restores it as either a double or a single.
2017-03-26 14:20:16 -07:00
Andrew Waterman
7180352067
Fix groundtest to provide missing signals to TLB
2017-03-26 14:20:16 -07:00
Andrew Waterman
5d1165c850
Express PMP mask generator using a carry chain
...
This allows it to be optimized like an adder, improving QoR when it
is on the critical path.
2017-03-26 14:20:16 -07:00
Andrew Waterman
bb42f3bf3b
WIP on FPU subword recoding
2017-03-26 14:20:16 -07:00
Wesley W. Terpstra
537274b645
coreplex: move buffers inside the coreplex
...
This should make hierarchical place and route easier.
2017-03-24 22:54:48 -07:00
Yunsup Lee
5bbb75e078
rename l2FrontendBus as fsb, expose bsb
2017-03-24 22:54:48 -07:00
Henry Cook
996a31364a
rocket: remove hard-coded paddrBits ( #610 )
...
Fall back on global variable but check that it is compatible with memory as seen from rocket's tilelink master port.
2017-03-24 22:30:18 -07:00
Wesley W. Terpstra
f36b1766f8
TLROM: use the smallest ROM implementation that works
...
The contents everywhere else are still zero.
2017-03-24 20:40:28 -07:00
Wesley W. Terpstra
ac205ca10a
bootrom: move to 0x10000 for more space (DTB on multicore is big)
2017-03-24 18:18:01 -07:00
Wesley W. Terpstra
34f8ce653a
bootrom: follow SBI (a0=hartid, a1=dtb)
2017-03-24 18:18:01 -07:00
Wesley W. Terpstra
9a2f0d01a1
GenerateBootROM: use compiled DTB
2017-03-24 18:18:01 -07:00
Andrew Waterman
17b1ee3037
Default to 8 PMPs; support 0 PMPs
2017-03-24 16:39:52 -07:00
Andrew Waterman
97006ab396
Don't modulate PMP privilege on passsthrough when !usingVM
2017-03-24 16:39:52 -07:00
Andrew Waterman
3f0d2fe826
Instantiate PTW unconditionally
...
This keeps the PMP datapaths intact. The PTW itself will get optimized
away for the !usingVM case.
2017-03-24 16:39:52 -07:00
Andrew Waterman
30415215b8
Don't check for exceptions on ScratchpadSlavePort accesses
2017-03-24 16:39:52 -07:00
Andrew Waterman
ccd5bc9a91
Improve QoR of PMP homogeneity checker
2017-03-24 16:39:52 -07:00
Andrew Waterman
e9cadf29d2
Improve DCache MMIO QoR
...
No need to store the cmd field. From the perspective of the cache, all
MMIO responses that have data can be treated the same as loads.
2017-03-24 16:39:52 -07:00
Andrew Waterman
fb6498f2c3
Use Reg(Vec) instead of Seq(Reg) for DCache MMIO
2017-03-24 16:39:52 -07:00
Andrew Waterman
0538dc77ce
For D$, use source 0 through N-1 for MMIO, not 1 through N
...
This makes the code a bit cleaner.
2017-03-24 16:39:52 -07:00
Andrew Waterman
3951e57789
Force each TLB entry into its own clock-gate group
...
This ameliorates a PMP critical path.
I can't figure out how to do this without asUInt/asTypeOf.
2017-03-24 16:39:52 -07:00
Andrew Waterman
8d7f1d777e
Fix an embarrassing typo in the PMPHeterogeneityChecker
2017-03-24 16:39:52 -07:00
Andrew Waterman
10c39cb8d6
Disable mprv in D-mode
2017-03-24 16:39:52 -07:00
Andrew Waterman
d3bda9574c
Put page homogeneity checker in PMP
...
Avoids redundancy between ITLB and DTLB
2017-03-24 16:39:52 -07:00
Andrew Waterman
9e05200e51
Don't require that PMP ranges be aligned to access size
...
e.g., if a range permits access to 0x0-0xb, allow 8-byte accesses 0x0-0x7.
2017-03-24 16:39:52 -07:00
Andrew Waterman
29e67279ba
add comments
2017-03-24 16:39:52 -07:00
Andrew Waterman
4c8be13a4d
Improve homogeneity circuit QoR
2017-03-24 16:39:52 -07:00
Andrew Waterman
59d6afa132
mideleg/medeleg not present without less-privileged traps
2017-03-24 16:39:52 -07:00
Andrew Waterman
38808f55d5
Share PMP mask gen between I$ and D$
2017-03-24 16:39:52 -07:00
Andrew Waterman
86d84959cf
More WIP on PMP
2017-03-24 16:39:52 -07:00
Andrew Waterman
2888779422
Flush pipeline from WB stage, not MEM
...
Fixes sptbr write -> instruction translation hazard.
2017-03-24 16:39:52 -07:00
Andrew Waterman
44ca3b60ab
Retime PTW response valid bits
...
It's not just to save the gate delay; it also reduces wire delay by
allowing the flops to be closer to their respective TLBs.
2017-03-24 16:39:52 -07:00
Andrew Waterman
a03556220c
Default TLB size = 32
...
@davidbiancolin
2017-03-24 16:39:52 -07:00
Andrew Waterman
1875407316
Get TLB permission checks off D$ clock gating critical path
2017-03-24 16:39:52 -07:00
Andrew Waterman
a4164348b4
Expose MXR to S-mode
2017-03-24 16:39:52 -07:00
Andrew Waterman
0380aed329
PUM -> SUM
2017-03-24 16:39:52 -07:00
Andrew Waterman
2a413e4496
Remove fruitless debug()
2017-03-24 16:39:52 -07:00
Andrew Waterman
29414f3a23
Simplify interrupt-stack discipline
...
f2ed45b179
2017-03-24 16:39:52 -07:00
Andrew Waterman
723352c3e2
Mitigate some more PMP critical paths
2017-03-24 16:39:52 -07:00
Andrew Waterman
7484f27ed3
Don't gate exception-cause pipeline registers separately
...
They are too narrow to justify gating separately from the other pipeline
registers (and one of the clock gates was on the PMP critical path).
2017-03-24 16:39:52 -07:00
Andrew Waterman
3ea822c2cf
Make blocking L1 D$ the default
...
The nonblocking cache is overdesigned for most Rocket-class cores, so
the blocking cache is the more appropriate default.
2017-03-24 16:39:52 -07:00
Andrew Waterman
487b8db5ef
Address some PMP critical paths
2017-03-24 16:39:52 -07:00
Andrew Waterman
03fb334c4c
Take mprv calculation off critical path
2017-03-24 16:39:52 -07:00
Andrew Waterman
f0796f0509
Pass correct access size information to PMP checker
2017-03-24 16:39:52 -07:00
Andrew Waterman
a6874c03f7
Remove DecoupledTLB
2017-03-24 16:39:52 -07:00
Andrew Waterman
78f9f6b9ef
When SFENCE.VMA has rs2 != x0, don't flush global mappings
2017-03-24 16:39:52 -07:00
Andrew Waterman
1b950128e1
PTW should always use S-mode privilege
...
If an exception occurs while a page-table walk is coincidentally in
progress (e.g., an illegal instruction executes during data TLB refill),
then the processor might enter M-mode. However, the PTW's accesses
should proceed without M privilege, to avoid bypassing PMPs.
Note, the same argument doesn't apply to the nonblocking cache's replay
queues, because those accesses have already been checked against the PMPs.
The cache correctly ignores access exceptions reported on replays,
provided no exceptions were reported on the initial access.
2017-03-24 16:39:52 -07:00
Andrew Waterman
aace526857
WIP on PMP
2017-03-24 16:39:52 -07:00
Andrew Waterman
b1b405404d
Set PRV=M when entering debug mode
...
Debug mode mostly behaves like M-mode, so this approach avoids having
to check the debug bit in most permission checks.
2017-03-24 16:39:52 -07:00
Andrew Waterman
cf168e419b
Support SFENCE.VMA rs1 argument
...
This one's a little invasive. To flush a specific entry from the TLB, you
need to reuse its CAM port. Since the TLB lookup can be on the critical
path, we wish to avoid muxing in another address.
This is simple on the data side, where the datapath already carries rs1 to
the TLB (it's the same path as the AMO address calculation). It's trickier
for the I$, where the TLB lookup address comes from the fetch stage PC.
The trick is to temporarily redirect the PC to rs1, then redirect the PC
again to the instruction after SFENCE.VMA.
2017-03-24 16:39:52 -07:00
Henry Cook
797c18b8db
Make some requirement failures more verbose ( #608 )
...
* tilelink: verbose requires in xbar
* diplomacy: verbose requires
2017-03-23 21:55:11 -07:00
Wesley W. Terpstra
bd08f10816
tilelink2: make sink ids optional ( #607 )
...
* tilelink2: make sink ids optional
* CacheCork: add a special-case for 1 sink id
2017-03-23 18:19:04 -07:00
Wesley W. Terpstra
19eb9b6906
l1tol2: put a flow Q on the exits ( #606 )
...
This Xbar connects the largest components in the design; the cores
and the L2 banks. We already have a full buffer on the core side.
However, the valid path going to the L2 comes back as a ready path.
Putting a flow Q also on the outputs of the l1tol2 cuts this path
in half at no cost to IPC.
2017-03-23 16:28:32 -07:00
Henry Cook
055b8ba1f0
rocket: avoid LinkedHashMap.keys to preserve traversal order ( #603 )
2017-03-22 14:38:33 -07:00
Andrew Waterman
76f083b469
FIFOFixer: Not all D-channel messages are A-channel responses
2017-03-21 14:17:38 -07:00
Andrew Waterman
3609254e4a
There's no structural hazard on MMIO store responses
...
So don't stall as though there were.
2017-03-21 14:17:32 -07:00
Yunsup Lee
5eae7e1da4
make DCache s1_nack less conservative for pipelined MMIO requests
2017-03-21 11:16:51 -07:00
Wesley W. Terpstra
4c00066746
rocket: describe dcache as two clients (fifo+cached)
2017-03-21 11:16:51 -07:00
Wesley W. Terpstra
81d717e82f
coreplex: guarantee FIFO for those tiles that need it
2017-03-21 11:16:51 -07:00
Wesley W. Terpstra
198afddb4b
tilelink2: add the FIFOFixer
2017-03-21 11:16:51 -07:00
Wesley W. Terpstra
c33f31dd3c
tilelink2 RAMModel: weaken fifo requirement check
2017-03-21 11:16:51 -07:00
Wesley W. Terpstra
930438adba
tilelink2 SourceShrinker: destroy FIFO behaviour
2017-03-21 11:16:51 -07:00
Wesley W. Terpstra
fd521c56a6
tilelink2: add client-side FIFO parameterization
2017-03-21 11:16:51 -07:00
Wesley W. Terpstra
4eef317e84
RegisterRouter: support devices with gaps
2017-03-20 14:49:22 -07:00
Wesley W. Terpstra
431cb41e27
tilelink2 Parameters: clarify client minLatency is B=>C, not D=>E
2017-03-20 14:49:22 -07:00
Wesley W. Terpstra
04892fea01
Monitor: support early ack
2017-03-20 14:49:19 -07:00
Wesley W. Terpstra
278f6fea24
tilelink2: define is{Request,Response} based on spec
2017-03-20 13:41:02 -07:00
Wesley W. Terpstra
778e189bba
Monitor: ProbeAckData and ReleaseData may carry an error
2017-03-20 11:44:13 -07:00
Wesley W. Terpstra
48c7aed4e1
Monitor: any probe supported by the client is legal
2017-03-20 11:34:19 -07:00
Wesley W. Terpstra
0c92283a61
rocket icache: tie off b ready
2017-03-19 17:18:50 -07:00
Wesley W. Terpstra
c9459fe4eb
tilelink2 Xbar: don't use unnecessary ports
2017-03-19 17:02:24 -07:00
Wesley W. Terpstra
7971947d6c
tilelink2 Monitor: don't inspect bits if valid is forbidden
2017-03-19 16:34:23 -07:00
Wesley W. Terpstra
a4ca424a22
AHBToTL: finally get the error signal right? ( #594 )
2017-03-18 22:24:20 -07:00
Wesley W. Terpstra
f6daa782d3
AHBToTL: fix the order of updates to d_pause ( #592 )
2017-03-17 19:34:40 -07:00
Megan Wachs
dcc9827ab4
Rename Prci.scala to Clint.scala ( #591 )
...
The internals of this were renamed to CoreplexLocalInterrupter, so changing the top level name to match.
2017-03-17 15:36:10 -07:00
Wesley W. Terpstra
db55a1d755
Fragmenter: fix a bug when underlying device supports larger bursts ( #589 )
2017-03-17 11:00:49 -07:00
Wesley W. Terpstra
9b5b3279a6
AHBToTL: don't report error during idle cycles
2017-03-16 18:18:29 -07:00
Wesley W. Terpstra
5efd38bf97
apb: put both aFlow options under regression
2017-03-16 15:36:14 -07:00
Wesley W. Terpstra
882a7ff8ff
TLToAPB: use the now standard aFlow parameter name
2017-03-16 15:34:59 -07:00
Wesley W. Terpstra
e31b84af33
axi4: use common BufferParams
2017-03-16 15:32:17 -07:00
Wesley W. Terpstra
ca2c709d29
TLBuffer: move TLBufferParams to diplomacy.BufferParams
2017-03-16 15:19:36 -07:00
Wesley W. Terpstra
778c8a5c97
ToAHB: appease AHB VIP
2017-03-16 15:17:05 -07:00
Wesley W. Terpstra
963d244094
unittest: try both aFlow settings of TLToAHB
2017-03-16 15:13:57 -07:00
Wesley W. Terpstra
604a164b97
TLToAHB: rename parameter to aFlow
2017-03-16 15:10:54 -07:00
Wesley W. Terpstra
bb49575368
ahb: rewrote TLToAHB to avoid retracting requests on stall
2017-03-16 14:36:30 -07:00
Wesley W. Terpstra
c95c2ca9c8
AHB: include bridge unit tests
2017-03-14 18:34:21 -07:00
Wesley W. Terpstra
0c5fd76089
ahb: implement a ToTL bridge
2017-03-14 18:34:17 -07:00
Wesley W. Terpstra
7f71df0925
apb: better test coverage
2017-03-14 18:34:17 -07:00
Wesley W. Terpstra
5885bf29b5
axi4: improve test harness
2017-03-14 18:34:17 -07:00
Wesley W. Terpstra
d98fd942f1
tilelink2: optimize the supportsX check circuits
2017-03-14 18:34:17 -07:00