rocket: separate page faults from physical memory access exceptions
This commit is contained in:
Andrew Waterman
parent
ea0714bfcb
commit
069858a20c
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@ -1 +1 @@
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Subproject commit 4f430b184ed07890cd30ad144ded6d7cb07dcdf0
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Subproject commit 89d487023c1e59ff574872e2f51ee479cda380ab
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@ -119,10 +119,15 @@ object CSR
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def R = UInt(5,SZ)
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val ADDRSZ = 12
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def debugIntCause = new MIP().getWidth
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def debugIntCause = {
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val res = 14
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require(res >= new MIP().getWidth)
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res
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}
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def debugTriggerCause = {
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require(debugIntCause >= Causes.all.max)
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debugIntCause
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val res = 14
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require(!(Causes.all contains res))
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res
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}
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val firstCtr = CSRs.cycle
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@ -224,10 +229,10 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
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}
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val delegable_exceptions = UInt(Seq(
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Causes.misaligned_fetch,
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Causes.fault_fetch,
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Causes.fetch_page_fault,
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Causes.breakpoint,
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Causes.fault_load,
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Causes.fault_store,
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Causes.load_page_fault,
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Causes.store_page_fault,
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Causes.user_ecall).map(1 << _).sum)
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val reg_debug = Reg(init=Bool(false))
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@ -483,7 +488,9 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
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val write_badaddr = cause isOneOf (Causes.breakpoint,
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Causes.misaligned_load, Causes.misaligned_store, Causes.misaligned_fetch,
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Causes.fault_load, Causes.fault_store, Causes.fault_fetch)
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Causes.load_access, Causes.store_access, Causes.fetch_access,
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Causes.load_page_fault, Causes.store_page_fault, Causes.fetch_page_fault
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)
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when (trapToDebug) {
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reg_debug := true
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@ -185,8 +185,10 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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val no_xcpt = Bool(usingDataScratchpad) && s1_req.phys /* slave port */ && s1_hit_state.isValid()
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io.cpu.xcpt.ma.ld := !no_xcpt && s1_read && s1_storegen.misaligned
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io.cpu.xcpt.ma.st := !no_xcpt && s1_write && s1_storegen.misaligned
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io.cpu.xcpt.pf.ld := !no_xcpt && s1_read && tlb.io.resp.xcpt_ld
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io.cpu.xcpt.pf.st := !no_xcpt && s1_write && tlb.io.resp.xcpt_st
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io.cpu.xcpt.pf.ld := !no_xcpt && s1_read && tlb.io.resp.pf.ld
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io.cpu.xcpt.pf.st := !no_xcpt && s1_write && tlb.io.resp.pf.st
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io.cpu.xcpt.ae.ld := !no_xcpt && s1_read && tlb.io.resp.ae.ld
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io.cpu.xcpt.ae.st := !no_xcpt && s1_write && tlb.io.resp.ae.st
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// load reservations
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val s2_lr = Bool(usingAtomics) && s2_req.cmd === M_XLR
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@ -22,7 +22,8 @@ class FrontendResp(implicit p: Parameters) extends CoreBundle()(p) {
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val pc = UInt(width = vaddrBitsExtended) // ID stage PC
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val data = UInt(width = fetchWidth * coreInstBits)
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val mask = Bits(width = fetchWidth)
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val xcpt_if = Bool()
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val pf = Bool()
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val ae = Bool()
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val replay = Bool()
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}
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@ -72,9 +73,12 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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val s2_pc = Reg(init=io.resetVector)
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val s2_btb_resp_valid = Reg(init=Bool(false))
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val s2_btb_resp_bits = Reg(new BTBResp)
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val s2_maybe_xcpt_if = Reg(init=Bool(false))
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val s2_maybe_pf = Reg(init=Bool(false))
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val s2_maybe_ae = Reg(init=Bool(false))
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val s2_tlb_miss = Reg(Bool())
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val s2_xcpt_if = s2_maybe_xcpt_if && !s2_tlb_miss
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val s2_pf = s2_maybe_pf && !s2_tlb_miss
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val s2_ae = s2_maybe_ae && !s2_tlb_miss
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val s2_xcpt = s2_pf || s2_ae
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val s2_speculative = Reg(init=Bool(false))
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val s2_cacheable = Reg(init=Bool(false))
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@ -101,7 +105,8 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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s2_pc := s1_pc
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s2_speculative := s1_speculative
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s2_cacheable := tlb.io.resp.cacheable
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s2_maybe_xcpt_if := tlb.io.resp.xcpt_if
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s2_maybe_pf := tlb.io.resp.pf.inst
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s2_maybe_ae := tlb.io.resp.ae.inst
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s2_tlb_miss := tlb.io.resp.miss
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}
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}
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@ -144,18 +149,19 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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icache.io.invalidate := io.cpu.flush_icache
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icache.io.s1_paddr := tlb.io.resp.paddr
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icache.io.s1_kill := io.cpu.req.valid || tlb.io.resp.miss || icmiss
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icache.io.s2_kill := s2_speculative && !s2_cacheable || s2_xcpt_if
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icache.io.s2_kill := s2_speculative && !s2_cacheable || s2_xcpt
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icache.io.resp.ready := !stall && !s1_same_block
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io.cpu.resp.valid := s2_valid && (icache.io.resp.valid || icache.io.s2_kill || s2_xcpt_if)
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io.cpu.resp.valid := s2_valid && (icache.io.resp.valid || icache.io.s2_kill || s2_xcpt)
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io.cpu.resp.bits.pc := s2_pc
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io.cpu.npc := Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc)
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require(fetchWidth * coreInstBytes <= rowBytes && isPow2(fetchWidth))
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io.cpu.resp.bits.data := icache.io.resp.bits.datablock >> (s2_pc.extract(log2Ceil(rowBytes)-1,log2Ceil(fetchWidth*coreInstBytes)) << log2Ceil(fetchWidth*coreInstBits))
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io.cpu.resp.bits.mask := UInt((1 << fetchWidth)-1) << s2_pc.extract(log2Ceil(fetchWidth)+log2Ceil(coreInstBytes)-1, log2Ceil(coreInstBytes))
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io.cpu.resp.bits.xcpt_if := s2_xcpt_if
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io.cpu.resp.bits.replay := icache.io.s2_kill && !icache.io.resp.valid && !s2_xcpt_if
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io.cpu.resp.bits.pf := s2_pf
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io.cpu.resp.bits.ae := s2_ae
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io.cpu.resp.bits.replay := icache.io.s2_kill && !icache.io.resp.valid && !s2_xcpt
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io.cpu.resp.bits.btb.valid := s2_btb_resp_valid
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io.cpu.resp.bits.btb.bits := s2_btb_resp_bits
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@ -113,6 +113,7 @@ class AlignmentExceptions extends Bundle {
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class HellaCacheExceptions extends Bundle {
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val ma = new AlignmentExceptions
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val pf = new AlignmentExceptions
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val ae = new AlignmentExceptions
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}
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// interface between D$ and processor/DTLB
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@ -11,6 +11,8 @@ import util._
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class Instruction(implicit val p: Parameters) extends ParameterizedBundle with HasCoreParameters {
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val pf0 = Bool() // page fault on first half of instruction
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val pf1 = Bool() // page fault on second half of instruction
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val ae0 = Bool() // access exception on first half of instruction
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val ae1 = Bool() // access exception on second half of instruction
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val replay = Bool()
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val btb_hit = Bool()
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val rvc = Bool()
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@ -78,7 +80,8 @@ class IBuf(implicit p: Parameters) extends CoreModule {
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val valid = (UIntToOH(nValid) - 1)(fetchWidth-1, 0)
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val bufMask = UIntToOH(nBufValid) - 1
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val xcpt_if = valid & (Mux(buf.xcpt_if, bufMask, UInt(0)) | Mux(io.imem.bits.xcpt_if, ~bufMask, UInt(0)))
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val pf = valid & (Mux(buf.pf, bufMask, UInt(0)) | Mux(io.imem.bits.pf, ~bufMask, UInt(0)))
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val ae = valid & (Mux(buf.ae, bufMask, UInt(0)) | Mux(io.imem.bits.ae, ~bufMask, UInt(0)))
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val ic_replay = valid & (Mux(buf.replay, bufMask, UInt(0)) | Mux(io.imem.bits.replay, ~bufMask, UInt(0)))
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val ibufBTBHitMask = Mux(ibufBTBHit, UIntToOH(ibufBTBResp.bridx), UInt(0))
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assert(!io.imem.bits.btb.valid || io.imem.bits.btb.bits.bridx >= pcWordBits)
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@ -97,9 +100,11 @@ class IBuf(implicit p: Parameters) extends CoreModule {
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if (usingCompressed) {
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val replay = ic_replay(j) || (!exp.io.rvc && (btbHitMask(j) || ic_replay(j+1)))
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io.inst(i).valid := valid(j) && (exp.io.rvc || valid(j+1) || xcpt_if(j+1) || replay)
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io.inst(i).bits.pf0 := xcpt_if(j)
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io.inst(i).bits.pf1 := !exp.io.rvc && xcpt_if(j+1)
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io.inst(i).valid := valid(j) && (exp.io.rvc || valid(j+1) || pf(j+1) || ae(j+1) || replay)
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io.inst(i).bits.pf0 := pf(j)
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io.inst(i).bits.pf1 := !exp.io.rvc && pf(j+1)
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io.inst(i).bits.ae0 := ae(j)
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io.inst(i).bits.ae1 := !exp.io.rvc && ae(j+1)
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io.inst(i).bits.replay := replay
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io.inst(i).bits.btb_hit := btbHitMask(j) || (!exp.io.rvc && btbHitMask(j+1))
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io.inst(i).bits.rvc := exp.io.rvc
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@ -110,8 +115,10 @@ class IBuf(implicit p: Parameters) extends CoreModule {
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} else {
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when (io.inst(i).ready) { nReady := i+1 }
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io.inst(i).valid := valid(i)
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io.inst(i).bits.pf0 := xcpt_if(i)
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io.inst(i).bits.pf0 := pf(i)
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io.inst(i).bits.pf1 := false
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io.inst(i).bits.ae0 := ae(i)
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io.inst(i).bits.ae1 := false
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io.inst(i).bits.replay := ic_replay(i)
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io.inst(i).bits.rvc := false
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io.inst(i).bits.btb_hit := btbHitMask(i)
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@ -216,31 +216,37 @@ object Instructions {
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}
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object Causes {
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val misaligned_fetch = 0x0
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val fault_fetch = 0x1
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val fetch_access = 0x1
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val illegal_instruction = 0x2
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val breakpoint = 0x3
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val misaligned_load = 0x4
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val fault_load = 0x5
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val load_access = 0x5
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val misaligned_store = 0x6
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val fault_store = 0x7
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val store_access = 0x7
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val user_ecall = 0x8
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val supervisor_ecall = 0x9
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val hypervisor_ecall = 0xa
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val machine_ecall = 0xb
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val fetch_page_fault = 0xc
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val load_page_fault = 0xd
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val store_page_fault = 0xf
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val all = {
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val res = collection.mutable.ArrayBuffer[Int]()
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res += misaligned_fetch
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res += fault_fetch
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res += fetch_access
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res += illegal_instruction
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res += breakpoint
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res += misaligned_load
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res += fault_load
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res += load_access
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res += misaligned_store
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res += fault_store
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res += store_access
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res += user_ecall
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res += supervisor_ecall
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res += hypervisor_ecall
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res += machine_ecall
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res += fetch_page_fault
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res += load_page_fault
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res += store_page_fault
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res.toArray
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}
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}
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@ -745,8 +745,10 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
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val misaligned = new StoreGen(s1_req.typ, s1_req.addr, UInt(0), wordBytes).misaligned
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io.cpu.xcpt.ma.ld := s1_read && misaligned
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io.cpu.xcpt.ma.st := s1_write && misaligned
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io.cpu.xcpt.pf.ld := s1_read && dtlb.io.resp.xcpt_ld
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io.cpu.xcpt.pf.st := s1_write && dtlb.io.resp.xcpt_st
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io.cpu.xcpt.pf.ld := s1_read && dtlb.io.resp.pf.ld
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io.cpu.xcpt.pf.st := s1_write && dtlb.io.resp.pf.st
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io.cpu.xcpt.ae.ld := s1_read && dtlb.io.resp.ae.ld
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io.cpu.xcpt.ae.st := s1_write && dtlb.io.resp.ae.st
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// tags
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def onReset = L1Metadata(UInt(0), ClientMetadata.onReset)
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@ -19,6 +19,7 @@ class PTWReq(implicit p: Parameters) extends CoreBundle()(p) {
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}
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class PTWResp(implicit p: Parameters) extends CoreBundle()(p) {
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val ae = Bool()
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val pte = new PTE
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val level = UInt(width = log2Ceil(pgLevels))
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val homogeneous = Bool()
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@ -77,7 +78,7 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
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val count = Reg(UInt(width = log2Up(pgLevels)))
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val s1_kill = Reg(next = Bool(false))
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val resp_valid = Reg(next = Vec.fill(io.requestor.size)(Bool(false)))
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val exception = Reg(next = io.mem.xcpt.pf.ld)
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val ae = Reg(next = io.mem.xcpt.ae.ld)
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val r_req = Reg(new PTWReq)
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val r_req_dest = Reg(Bits())
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@ -90,14 +91,15 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
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arb.io.in <> io.requestor.map(_.req)
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arb.io.out.ready := state === s_ready
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val pte = {
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val (pte, invalid_paddr) = {
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val tmp = new PTE().fromBits(io.mem.resp.bits.data)
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val res = Wire(init = new PTE().fromBits(io.mem.resp.bits.data))
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res.ppn := tmp.ppn(ppnBits-1, 0)
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when ((tmp.ppn >> ppnBits) =/= 0) { res.v := false }
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res
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(res, (tmp.ppn >> ppnBits) =/= 0)
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}
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val traverse = pte.table() && !invalid_paddr && count < pgLevels-1
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val pte_addr = Cat(r_pte.ppn, vpn_idx) << log2Ceil(xLen/8)
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val resp_ae = Reg(next = ae || invalid_paddr)
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when (arb.io.out.fire()) {
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r_req := arb.io.out.bits
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@ -114,7 +116,7 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
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val hits = tags.map(_ === pte_addr).asUInt & valid
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val hit = hits.orR
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when (io.mem.resp.valid && pte.table() && !hit) {
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when (io.mem.resp.valid && traverse && !hit) {
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val r = Mux(valid.andR, plru.replace, PriorityEncoder(~valid))
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valid := valid | UIntToOH(r)
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tags(r) := pte_addr
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@ -142,6 +144,7 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
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for (i <- 0 until io.requestor.size) {
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io.requestor(i).resp.valid := resp_valid(i)
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io.requestor(i).resp.bits.ae := resp_ae
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io.requestor(i).resp.bits.pte := r_pte
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io.requestor(i).resp.bits.level := count
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io.requestor(i).resp.bits.pte.ppn := pte_addr >> pgIdxBits
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@ -177,16 +180,17 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
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}
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when (io.mem.resp.valid) {
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r_pte := pte
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when (pte.table() && count < pgLevels-1) {
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when (traverse) {
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state := s_req
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count := count + 1
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}.otherwise {
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resp_ae := invalid_paddr
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state := s_ready
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resp_valid(r_req_dest) := true
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}
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}
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when (exception) {
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r_pte.v := false
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when (ae) {
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resp_ae := true
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state := s_ready
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resp_valid(r_req_dest) := true
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}
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@ -225,12 +225,14 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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bpu.io.pc := ibuf.io.pc
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bpu.io.ea := mem_reg_wdata
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val id_xcpt_if = ibuf.io.inst(0).bits.pf0 || ibuf.io.inst(0).bits.pf1
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val id_xcpt_pf = ibuf.io.inst(0).bits.pf0 || ibuf.io.inst(0).bits.pf1
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val id_xcpt_ae = ibuf.io.inst(0).bits.ae0 || ibuf.io.inst(0).bits.ae1
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val (id_xcpt, id_cause) = checkExceptions(List(
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(csr.io.interrupt, csr.io.interrupt_cause),
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(bpu.io.debug_if, UInt(CSR.debugTriggerCause)),
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(bpu.io.xcpt_if, UInt(Causes.breakpoint)),
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(id_xcpt_if, UInt(Causes.fault_fetch)),
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(id_xcpt_pf, UInt(Causes.fetch_page_fault)),
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(id_xcpt_ae, UInt(Causes.fetch_access)),
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(id_illegal_insn, UInt(Causes.illegal_instruction))))
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val dcache_bypass_data =
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@ -423,8 +425,10 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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val (wb_xcpt, wb_cause) = checkExceptions(List(
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(wb_reg_xcpt, wb_reg_cause),
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(wb_reg_valid && wb_ctrl.mem && RegEnable(io.dmem.xcpt.pf.st, mem_pc_valid), UInt(Causes.fault_store)),
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(wb_reg_valid && wb_ctrl.mem && RegEnable(io.dmem.xcpt.pf.ld, mem_pc_valid), UInt(Causes.fault_load))
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(wb_reg_valid && wb_ctrl.mem && RegEnable(io.dmem.xcpt.pf.st, mem_pc_valid), UInt(Causes.store_page_fault)),
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(wb_reg_valid && wb_ctrl.mem && RegEnable(io.dmem.xcpt.pf.ld, mem_pc_valid), UInt(Causes.load_page_fault)),
|
||||
(wb_reg_valid && wb_ctrl.mem && RegEnable(io.dmem.xcpt.ae.st, mem_pc_valid), UInt(Causes.store_access)),
|
||||
(wb_reg_valid && wb_ctrl.mem && RegEnable(io.dmem.xcpt.ae.ld, mem_pc_valid), UInt(Causes.load_access))
|
||||
))
|
||||
|
||||
val wb_wxd = wb_reg_valid && wb_ctrl.wxd
|
||||
|
|
|
|||
|
|
@ -33,20 +33,25 @@ class TLBReq(lgMaxSize: Int)(implicit p: Parameters) extends CoreBundle()(p) {
|
|||
override def cloneType = new TLBReq(lgMaxSize).asInstanceOf[this.type]
|
||||
}
|
||||
|
||||
class TLBExceptions extends Bundle {
|
||||
val ld = Bool()
|
||||
val st = Bool()
|
||||
val inst = Bool()
|
||||
}
|
||||
|
||||
class TLBResp(implicit p: Parameters) extends CoreBundle()(p) {
|
||||
// lookup responses
|
||||
val miss = Bool(OUTPUT)
|
||||
val paddr = UInt(OUTPUT, paddrBits)
|
||||
val xcpt_ld = Bool(OUTPUT)
|
||||
val xcpt_st = Bool(OUTPUT)
|
||||
val xcpt_if = Bool(OUTPUT)
|
||||
val cacheable = Bool(OUTPUT)
|
||||
val miss = Bool()
|
||||
val paddr = UInt(width = paddrBits)
|
||||
val pf = new TLBExceptions
|
||||
val ae = new TLBExceptions
|
||||
val cacheable = Bool()
|
||||
}
|
||||
|
||||
class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) {
|
||||
val io = new Bundle {
|
||||
val req = Decoupled(new TLBReq(lgMaxSize)).flip
|
||||
val resp = new TLBResp
|
||||
val resp = new TLBResp().asOutput
|
||||
val ptw = new TLBPTWIO
|
||||
}
|
||||
|
||||
|
|
@ -59,8 +64,10 @@ class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters
|
|||
val sw = Bool()
|
||||
val sx = Bool()
|
||||
val sr = Bool()
|
||||
val xr = Bool()
|
||||
val cacheable = Bool()
|
||||
val pw = Bool()
|
||||
val px = Bool()
|
||||
val pr = Bool()
|
||||
val c = Bool()
|
||||
}
|
||||
|
||||
val totalEntries = nEntries + 1
|
||||
|
|
@ -101,7 +108,7 @@ class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters
|
|||
val prot_w = fastCheck(_.supportsPutFull) && pmp.io.w
|
||||
val prot_x = fastCheck(_.executable) && pmp.io.x
|
||||
val cacheable = fastCheck(_.supportsAcquireB)
|
||||
val isSpecial = !io.ptw.resp.bits.homogeneous
|
||||
val isSpecial = !(io.ptw.resp.bits.homogeneous || io.ptw.resp.bits.ae)
|
||||
|
||||
val lookup_tag = Cat(io.ptw.ptbr.asid, vpn(vpnBits-1,0))
|
||||
val hitsVec = (0 until totalEntries).map { i => vm_enabled && {
|
||||
|
|
@ -123,13 +130,6 @@ class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters
|
|||
}
|
||||
|
||||
// permission bit arrays
|
||||
val u_array = Reg(Vec(totalEntries, Bool())) // user permission
|
||||
val g_array = Reg(Vec(totalEntries, Bool())) // global mapping
|
||||
val sw_array = Reg(Vec(totalEntries, Bool())) // write permission
|
||||
val sx_array = Reg(Vec(totalEntries, Bool())) // execute permission
|
||||
val sr_array = Reg(Vec(totalEntries, Bool())) // read permission
|
||||
val xr_array = Reg(Vec(totalEntries, Bool())) // read permission to executable page
|
||||
val cash_array = Reg(Vec(normalEntries, Bool())) // cacheable
|
||||
when (do_refill && !invalidate_refill) {
|
||||
val waddr = Mux(isSpecial, specialEntry.U, r_refill_waddr)
|
||||
val pte = io.ptw.resp.bits.pte
|
||||
|
|
@ -137,13 +137,15 @@ class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters
|
|||
newEntry.ppn := pte.ppn
|
||||
newEntry.tag := r_refill_tag
|
||||
newEntry.level := io.ptw.resp.bits.level
|
||||
newEntry.c := cacheable
|
||||
newEntry.u := pte.u
|
||||
newEntry.g := pte.g
|
||||
newEntry.sw := pte.sw() && (isSpecial || prot_w)
|
||||
newEntry.sx := pte.sx() && (isSpecial || prot_x)
|
||||
newEntry.sr := pte.sr() && (isSpecial || prot_r)
|
||||
newEntry.xr := pte.sx() && (isSpecial || prot_r)
|
||||
newEntry.cacheable := isSpecial || cacheable
|
||||
newEntry.sr := pte.sr()
|
||||
newEntry.sw := pte.sw()
|
||||
newEntry.sx := pte.sx()
|
||||
newEntry.pr := prot_r && !io.ptw.resp.bits.ae
|
||||
newEntry.pw := prot_w && !io.ptw.resp.bits.ae
|
||||
newEntry.px := prot_x && !io.ptw.resp.bits.ae
|
||||
|
||||
valid := valid | UIntToOH(waddr)
|
||||
reg_entries(waddr) := newEntry.asUInt
|
||||
|
|
@ -153,10 +155,13 @@ class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters
|
|||
val repl_waddr = Mux(!valid(normalEntries-1, 0).andR, PriorityEncoder(~valid(normalEntries-1, 0)), plru.replace)
|
||||
|
||||
val priv_ok = Mux(priv_s, ~Mux(io.ptw.status.sum, UInt(0), entries.map(_.u).asUInt), entries.map(_.u).asUInt)
|
||||
val w_array = Cat(prot_w, priv_ok & ~(~prot_w << specialEntry) & entries.map(_.sw).asUInt)
|
||||
val x_array = Cat(prot_x, priv_ok & ~(~prot_x << specialEntry) & entries.map(_.sx).asUInt)
|
||||
val r_array = Cat(prot_r, priv_ok & ~(~prot_r << specialEntry) & (entries.map(_.sr).asUInt | Mux(io.ptw.status.mxr, entries.map(_.xr).asUInt, UInt(0))))
|
||||
val c_array = Cat(cacheable, ~(~cacheable << specialEntry) & entries.map(_.cacheable).asUInt)
|
||||
val r_array = Cat(true.B, priv_ok & (entries.map(_.sr).asUInt | Mux(io.ptw.status.mxr, entries.map(_.sx).asUInt, UInt(0))))
|
||||
val w_array = Cat(true.B, priv_ok & entries.map(_.sw).asUInt)
|
||||
val x_array = Cat(true.B, priv_ok & entries.map(_.sx).asUInt)
|
||||
val pr_array = Cat(Fill(2, prot_r), entries.init.map(_.pr).asUInt)
|
||||
val pw_array = Cat(Fill(2, prot_w), entries.init.map(_.pw).asUInt)
|
||||
val px_array = Cat(Fill(2, prot_x), entries.init.map(_.px).asUInt)
|
||||
val c_array = Cat(Fill(2, cacheable), entries.init.map(_.c).asUInt)
|
||||
|
||||
val bad_va =
|
||||
if (vpnBits == vpnBitsExtended) Bool(false)
|
||||
|
|
@ -176,9 +181,12 @@ class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters
|
|||
val multipleHits = PopCountAtLeast(hits(totalEntries-1, 0), 2)
|
||||
|
||||
io.req.ready := state === s_ready
|
||||
io.resp.xcpt_ld := bad_va || (~r_array & hits).orR
|
||||
io.resp.xcpt_st := bad_va || (~w_array & hits).orR
|
||||
io.resp.xcpt_if := bad_va || (~x_array & hits).orR
|
||||
io.resp.pf.ld := bad_va || (~r_array & hits).orR
|
||||
io.resp.pf.st := bad_va || (~w_array & hits).orR
|
||||
io.resp.pf.inst := bad_va || (~x_array & hits).orR
|
||||
io.resp.ae.ld := (~pr_array & hits).orR
|
||||
io.resp.ae.st := (~pw_array & hits).orR
|
||||
io.resp.ae.inst := (~px_array & hits).orR
|
||||
io.resp.cacheable := (c_array & hits).orR
|
||||
io.resp.miss := do_refill || tlb_miss || multipleHits
|
||||
io.resp.paddr := Cat(ppn, pgOffset)
|
||||
|
|
@ -208,7 +216,7 @@ class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters
|
|||
|
||||
when (sfence) {
|
||||
valid := Mux(io.req.bits.sfence.bits.rs1, valid & ~hits(totalEntries-1, 0),
|
||||
Mux(io.req.bits.sfence.bits.rs2, valid & g_array.asUInt, 0))
|
||||
Mux(io.req.bits.sfence.bits.rs2, valid & entries.map(_.g).asUInt, 0))
|
||||
}
|
||||
when (multipleHits) {
|
||||
valid := 0
|
||||
|
|
|
|||
Loading…
Reference in New Issue