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debug: DMI response should be busy, not zero, when there is an error. (#685)

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This commit is contained in:
Megan Wachs
2017-04-18 21:41:52 -07:00
committed by GitHub
parent d82a0dc231
commit 408107447c
1 changed files with 1 additions and 1 deletions
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src/main/scala/rocketchip/DebugTransport.scala
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@@ -159,7 +159,7 @@ class DebugTransportModuleJTAG(debugAddrBits: Int, c: JtagDTMConfig)
nonzeroResp := stickyNonzeroRespReg | (io.dmi.resp.valid & (io.dmi.resp.bits.resp != UInt(0)))
busyResp.addr := UInt(0)
busyResp.resp := UInt(0)
busyResp.resp := -1.S(DMIConsts.dmiRespSize.W).asUInt // Generalizing busy to 'all-F'
busyResp.data := UInt(0)
nonbusyResp.addr := dmiReqReg.addr