Implement new FP encoding proposal
Single-precision values are stored in the regfile as double-precision, so that FSD on a single-precision value stores a proper double and FLD restores it as either a double or a single.
This commit is contained in:
Andrew Waterman
Andrew Waterman
parent
7180352067
commit
e710e32f10
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@ -222,13 +222,11 @@ object ClassifyRecFN {
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}
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object IsNaNRecFN {
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def apply(expWidth: Int, sigWidth: Int, in: UInt) =
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in(sigWidth + expWidth - 1, sigWidth + expWidth - 3).andR
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def apply(in: UInt, t: FType) = in(t.sig + t.exp - 1, t.sig + t.exp - 3).andR
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}
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object IsSNaNRecFN {
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def apply(expWidth: Int, sigWidth: Int, in: UInt) =
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IsNaNRecFN(expWidth, sigWidth, in) && !in(sigWidth - 2)
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def apply(in: UInt, t: FType) = IsNaNRecFN(in, t) && !in(t.sig - 2)
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}
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class FType(val exp: Int, val sig: Int)
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@ -273,6 +271,9 @@ trait HasFPUParameters {
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val maxType = floatTypes.sortWith(_.exp > _.exp).head
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val maxExpWidth = maxType.exp
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val maxSigWidth = maxType.sig
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def expand(x: UInt, t: FType) = RecFNToRecFN_noncompliant(x, t.exp, t.sig, maxType.exp, maxType.sig)
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def contract(x: UInt, t: FType) = RecFNToRecFN_noncompliant(x, maxType.exp, maxType.sig, t.exp, t.sig)
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}
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abstract class FPUModule(implicit p: Parameters) extends CoreModule()(p) with HasFPUParameters
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@ -291,20 +292,11 @@ class FPToInt(implicit p: Parameters) extends FPUModule()(p) {
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val out = Valid(new Output)
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}
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val in = Reg(new FPInput)
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val in = RegEnable(io.in.bits, io.in.valid)
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val valid = Reg(next=io.in.valid)
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def upconvert(x: UInt) = RecFNToRecFN_noncompliant(x, sExpWidth, sSigWidth, maxExpWidth, maxSigWidth)
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when (io.in.valid) {
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in := io.in.bits
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if (fLen > 32) when (io.in.bits.single && !io.in.bits.ldst && io.in.bits.cmd =/= FCMD_MV_XF) {
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in.in1 := upconvert(io.in.bits.in1)
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in.in2 := upconvert(io.in.bits.in2)
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}
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}
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val unrec_s = hardfloat.fNFromRecFN(sExpWidth, sSigWidth, in.in1).sextTo(xLen)
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val in1_s = contract(in.in1, FType.S)
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val unrec_s = hardfloat.fNFromRecFN(sExpWidth, sSigWidth, in1_s).sextTo(xLen)
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val unrec_mem = fLen match {
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case 32 => unrec_s
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case 64 =>
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@ -316,7 +308,7 @@ class FPToInt(implicit p: Parameters) extends FPUModule()(p) {
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case fLen => unrec_mem
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}
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val classify_s = ClassifyRecFN(sExpWidth, sSigWidth, in.in1)
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val classify_s = ClassifyRecFN(sExpWidth, sSigWidth, in1_s)
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val classify_out = fLen match {
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case 32 => classify_s
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case 64 =>
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@ -367,7 +359,7 @@ class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) {
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val mux = Wire(new FPResult)
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mux.exc := Bits(0)
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mux.data := hardfloat.recFNFromFN(sExpWidth, sSigWidth, in.bits.in1)
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mux.data := expand(hardfloat.recFNFromFN(sExpWidth, sSigWidth, in.bits.in1), FType.S)
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if (fLen > 32) when (!in.bits.single) {
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mux.data := hardfloat.recFNFromFN(dExpWidth, dSigWidth, in.bits.in1)
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}
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@ -390,67 +382,51 @@ class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) {
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l2s.io.signedIn := ~in.bits.typ(0)
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l2s.io.in := intValue
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l2s.io.roundingMode := in.bits.rm
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mux.data := expand(l2s.io.out, FType.S)
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mux.exc := l2s.io.exceptionFlags
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fLen match {
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case 32 =>
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mux.data := l2s.io.out
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mux.exc := l2s.io.exceptionFlags
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case 64 =>
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val l2d = Module(new hardfloat.INToRecFN(xLen, dExpWidth, dSigWidth))
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l2d.io.signedIn := ~in.bits.typ(0)
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l2d.io.in := intValue
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l2d.io.roundingMode := in.bits.rm
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mux.data := Cat(l2d.io.out >> l2s.io.out.getWidth, l2s.io.out)
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mux.exc := l2s.io.exceptionFlags
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when (!in.bits.single) {
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mux.data := l2d.io.out
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mux.exc := l2d.io.exceptionFlags
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}
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}
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}
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io.out <> Pipe(in.valid, mux, latency-1)
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}
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class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) {
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val io = new Bundle {
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val in = Valid(new FPInput).flip
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val out = Valid(new FPResult)
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val lt = Bool(INPUT) // from FPToInt
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}
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io.out <> Pipe(in.valid, mux, latency-1)
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}
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val in = Pipe(io.in)
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class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) {
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val io = new Bundle {
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val in = Valid(new FPInput).flip
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val out = Valid(new FPResult)
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val lt = Bool(INPUT) // from FPToInt
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}
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val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))
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val fsgnj_s = Cat(signNum(32), in.bits.in1(31, 0))
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val fsgnj = fLen match {
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case 32 => fsgnj_s
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case 64 => Mux(in.bits.single, Cat(in.bits.in1 >> 33, fsgnj_s),
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Cat(signNum(64), in.bits.in1(63, 0)))
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}
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val mux = Wire(new FPResult)
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mux.exc := UInt(0)
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mux.data := fsgnj
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val in = Pipe(io.in)
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when (in.bits.cmd === FCMD_MINMAX) {
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def doMinMax(expWidth: Int, sigWidth: Int) = {
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val isnan1 = IsNaNRecFN(expWidth, sigWidth, in.bits.in1)
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val isnan2 = IsNaNRecFN(expWidth, sigWidth, in.bits.in2)
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val issnan1 = IsSNaNRecFN(expWidth, sigWidth, in.bits.in1)
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val issnan2 = IsSNaNRecFN(expWidth, sigWidth, in.bits.in2)
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val invalid = issnan1 || issnan2
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val isNaNOut = invalid || (isnan1 && isnan2)
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val cNaN = floatTypes.filter(_.exp >= expWidth).map(CanonicalNaN(_)).reduce(_+_)
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(isnan2 || in.bits.rm(0) =/= io.lt && !isnan1, invalid, isNaNOut, cNaN)
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}
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val (isLHS, isInvalid, isNaNOut, cNaN) = fLen match {
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case 32 => doMinMax(sExpWidth, sSigWidth)
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case 64 => MuxT(in.bits.single, doMinMax(sExpWidth, sSigWidth), doMinMax(dExpWidth, dSigWidth))
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}
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mux.exc := isInvalid << 4
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mux.data := Mux(isNaNOut, cNaN, Mux(isLHS, in.bits.in1, in.bits.in2))
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}
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val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))
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val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))
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val mux = Wire(new FPResult)
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mux.exc := UInt(0)
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mux.data := fsgnj
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when (in.bits.cmd === FCMD_MINMAX) {
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val isnan1 = IsNaNRecFN(in.bits.in1, maxType)
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val isnan2 = IsNaNRecFN(in.bits.in2, maxType)
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val isInvalid = IsSNaNRecFN(in.bits.in1, maxType) || IsSNaNRecFN(in.bits.in2, maxType)
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val isNaNOut = isInvalid || (isnan1 && isnan2)
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val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1
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mux.exc := isInvalid << 4
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mux.data := Mux(isNaNOut, CanonicalNaN(maxType), Mux(isLHS, in.bits.in1, in.bits.in2))
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}
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fLen match {
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case 32 =>
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@ -461,11 +437,11 @@ class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) {
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d2s.io.roundingMode := in.bits.rm
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val s2d = Module(new hardfloat.RecFNToRecFN(sExpWidth, sSigWidth, dExpWidth, dSigWidth))
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s2d.io.in := in.bits.in1
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s2d.io.in := contract(in.bits.in1, FType.S)
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s2d.io.roundingMode := in.bits.rm
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when (in.bits.single) {
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mux.data := Cat(s2d.io.out >> d2s.io.out.getWidth, d2s.io.out)
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mux.data := expand(d2s.io.out, FType.S)
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mux.exc := d2s.io.exceptionFlags
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}.otherwise {
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mux.data := s2d.io.out
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@ -477,28 +453,29 @@ class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) {
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io.out <> Pipe(in.valid, mux, latency-1)
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}
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class FPUFMAPipe(val latency: Int, expWidth: Int, sigWidth: Int)(implicit p: Parameters) extends FPUModule()(p) {
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class FPUFMAPipe(val latency: Int, t: FType)(implicit p: Parameters) extends FPUModule()(p) {
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val io = new Bundle {
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val in = Valid(new FPInput).flip
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val out = Valid(new FPResult)
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}
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val width = sigWidth + expWidth
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val width = t.sig + t.exp
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val one = UInt(1) << (width-1)
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val zero = (io.in.bits.in1(width) ^ io.in.bits.in2(width)) << width
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val valid = Reg(next=io.in.valid)
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val in = Reg(new FPInput)
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when (io.in.valid) {
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in := io.in.bits
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val cmd_fma = io.in.bits.ren3
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val cmd_addsub = io.in.bits.swap23
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in := io.in.bits
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in.in1 := contract(io.in.bits.in1, t)
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in.in2 := Mux(cmd_addsub, one, contract(io.in.bits.in2, t))
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in.in3 := Mux(cmd_fma || cmd_addsub, contract(io.in.bits.in3, t), zero)
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in.cmd := Cat(io.in.bits.cmd(1) & (cmd_fma || cmd_addsub), io.in.bits.cmd(0))
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when (cmd_addsub) { in.in2 := one }
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unless (cmd_fma || cmd_addsub) { in.in3 := zero }
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}
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val fma = Module(new hardfloat.MulAddRecFN(expWidth, sigWidth))
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val fma = Module(new hardfloat.MulAddRecFN(t.exp, t.sig))
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fma.io.op := in.cmd
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fma.io.roundingMode := in.rm
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fma.io.a := in.in1
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@ -506,7 +483,7 @@ class FPUFMAPipe(val latency: Int, expWidth: Int, sigWidth: Int)(implicit p: Par
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fma.io.c := in.in3
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val res = Wire(new FPResult)
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res.data := fma.io.out
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res.data := expand(fma.io.out, t)
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res.exc := fma.io.exceptionFlags
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io.out := Pipe(valid, res, latency-1)
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}
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@ -538,9 +515,6 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
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val mem_ctrl = RegEnable(ex_ctrl, req_valid)
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val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)
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def expand(x: UInt, t: FType) = RecFNToRecFN_noncompliant(x, t.exp, t.sig, maxType.exp, maxType.sig)
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def contract(x: UInt, t: FType) = RecFNToRecFN_noncompliant(x, maxType.exp, maxType.sig, t.exp, t.sig)
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// load response
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val load_wb = Reg(next=io.dmem_resp_val)
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val load_wb_single = RegEnable(!io.dmem_resp_type(0), io.dmem_resp_val)
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@ -551,7 +525,7 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
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case 32 => rec_s
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case 64 =>
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val rec_d = hardfloat.recFNFromFN(dExpWidth, dSigWidth, load_wb_data)
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Mux(load_wb_single, rec_s | CanonicalNaN.signaling(maxType), rec_d)
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Mux(load_wb_single, expand(rec_s, FType.S), rec_d)
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}
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// regfile
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@ -592,7 +566,7 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
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}
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}
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val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, sExpWidth, sSigWidth))
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val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))
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sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.single
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sfma.io.in.bits := req
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@ -632,7 +606,7 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
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Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),
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Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.single, sfma.io.out.bits)) ++
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(fLen > 32).option({
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val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, dExpWidth, dSigWidth))
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val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))
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dfma.io.in.valid := req_valid && ex_ctrl.fma && !ex_ctrl.single
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dfma.io.in.bits := req
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Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && !c.single, dfma.io.out.bits)
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@ -677,17 +651,13 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
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}
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val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)
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val wdata0 = Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid))
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val wsingle = Mux(divSqrt_wen, divSqrt_single, wbInfo(0).single)
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val wdata = fLen match {
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case 32 => wdata0
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case 64 => Mux(wsingle, wdata0(32, 0) | CanonicalNaN.signaling(maxType), wdata0)
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}
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val wdata = Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid))
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val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)
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when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {
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regfile(waddr) := wdata
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if (enableCommitLog) {
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val wdata_unrec_s = hardfloat.fNFromRecFN(sExpWidth, sSigWidth, wdata)
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val wsingle = Mux(divSqrt_wen, divSqrt_single, wbInfo(0).single)
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val wdata_unrec_s = hardfloat.fNFromRecFN(sExpWidth, sSigWidth, contract(wdata, FType.S))
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val unrec = fLen match {
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case 32 => wdata_unrec_s
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case 64 =>
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@ -757,7 +727,7 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
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val divSqrt_toSingle = Module(new hardfloat.RecFNToRecFN(11, 53, 8, 24))
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divSqrt_toSingle.io.in := divSqrt_wdata_double
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divSqrt_toSingle.io.roundingMode := divSqrt_rm
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divSqrt_wdata := Mux(divSqrt_single, divSqrt_toSingle.io.out, divSqrt_wdata_double)
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divSqrt_wdata := Mux(divSqrt_single, expand(divSqrt_toSingle.io.out, FType.S), divSqrt_wdata_double)
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divSqrt_flags := divSqrt_flags_double | Mux(divSqrt_single, divSqrt_toSingle.io.exceptionFlags, Bits(0))
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} else {
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when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true }
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