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When not using a cache, LR/SC isn't legal even on cacheable memory

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Andrew Waterman 2017-04-19 16:52:23 -07:00 committed by Megan Wachs
parent 1be13d6b4c
commit 67404a665b
1 changed files with 2 additions and 1 deletions
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3
src/main/scala/rocket/TLB.scala
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@ -188,9 +188,10 @@ class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters
(if (vpnBits == vpnBitsExtended) Bool(false)
else vpn(vpnBits) =/= vpn(vpnBits-1))
val lrscAllowed = Mux(Bool(usingDataScratchpad), 0.U, c_array)
val ae_array =
Mux(misaligned, eff_array, 0.U) |
Mux(Bool(usingAtomics) && io.req.bits.cmd.isOneOf(M_XLR, M_XSC), ~c_array, 0.U)
Mux(Bool(usingAtomics) && io.req.bits.cmd.isOneOf(M_XLR, M_XSC), ~lrscAllowed, 0.U)
val ae_ld_array = Mux(isRead(io.req.bits.cmd), ae_array | ~pr_array, 0.U)
val ae_st_array =
Mux(isWrite(io.req.bits.cmd), ae_array | ~pw_array, 0.U) |