riscv/rocket-chip
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Mitigate D$ exception critical path, yet again

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Andrew Waterman 2017-04-17 23:48:30 -07:00 committed by Andrew Waterman
parent c99ce7ce5d
commit d82a0dc231
2 changed files with 6 additions and 4 deletions
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5
src/main/scala/rocket/DCache.scala
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@ -480,8 +480,9 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
io.cpu.resp.bits.replay := false
io.cpu.ordered := !(s1_valid || s2_valid || cached_grant_wait || uncachedInFlight.asUInt.orR)
val s1_xcpt = Mux(s1_nack || !tlb.io.req.valid, 0.U.asTypeOf(tlb.io.resp), tlb.io.resp)
io.cpu.s2_xcpt := RegEnable(s1_xcpt, s1_valid)
val s1_xcpt_valid = tlb.io.req.valid && !s1_nack
val s1_xcpt = tlb.io.resp
io.cpu.s2_xcpt := Mux(RegNext(s1_xcpt_valid), RegEnable(s1_xcpt, s1_valid_not_nacked), 0.U.asTypeOf(s1_xcpt))
// uncached response
io.cpu.replay_next := tl_out.d.fire() && grantIsUncachedData

5
src/main/scala/rocket/NBDcache.scala
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@ -975,8 +975,9 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
io.cpu.ordered := mshrs.io.fence_rdy && !s1_valid && !s2_valid
io.cpu.replay_next := (s1_replay && s1_read) || mshrs.io.replay_next
val s1_xcpt = Mux(s1_nack || !dtlb.io.req.valid, 0.U.asTypeOf(dtlb.io.resp), dtlb.io.resp)
io.cpu.s2_xcpt := RegEnable(s1_xcpt, s1_clk_en)
val s1_xcpt_valid = dtlb.io.req.valid && !s1_nack
val s1_xcpt = dtlb.io.resp
io.cpu.s2_xcpt := Mux(RegNext(s1_xcpt_valid), RegEnable(s1_xcpt, s1_clk_en), 0.U.asTypeOf(s1_xcpt))
// performance events
io.cpu.acquire := edge.done(tl_out.a)