ahb: rewrote TLToAHB to avoid retracting requests on stall
This commit is contained in:
Wesley W. Terpstra
parent
4f5f686c7e
commit
bb49575368
@ -25,12 +25,29 @@ case class TLToAHBNode() extends MixedAdapterNode(TLImp, AHBImp)(
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nodePath = s.nodePath,
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supportsGet = s.supportsRead,
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supportsPutFull = s.supportsWrite, // but not PutPartial
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fifoId = Some(0)) // a common FIFO domain
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fifoId = Some(0))
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}
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TLManagerPortParameters(managers, beatBytes, 1, 1)
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})
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class TLToAHB(val combinational: Boolean = true)(implicit p: Parameters) extends LazyModule
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class AHBControlBundle(params: TLEdge) extends util.GenericParameterizedBundle(params)
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{
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val full = Bool()
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val send = Bool() // => full+data
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val first = Bool()
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val last = Bool()
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val write = Bool()
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val size = UInt(width = params.bundle.sizeBits)
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val source = UInt(width = params.bundle.sourceBits)
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val hsize = UInt(width = AHBParameters.sizeBits)
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val hburst = UInt(width = AHBParameters.burstBits)
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val addr = UInt(width = params.bundle.addressBits)
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val data = UInt(width = params.bundle.dataBits)
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}
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// The input side has either a flow queue (a_pipe=false) or a pipe queue (a_pipe=true)
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// The output side always has a flow queue
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class TLToAHB(val a_pipe: Boolean = true)(implicit p: Parameters) extends LazyModule
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{
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val node = TLToAHBNode()
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@ -40,88 +57,131 @@ class TLToAHB(val combinational: Boolean = true)(implicit p: Parameters) extends
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val out = node.bundleOut
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}
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((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
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((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
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val beatBytes = edgeOut.slave.beatBytes
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val maxTransfer = edgeOut.slave.maxTransfer
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val lgMax = log2Ceil(maxTransfer)
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val lgBytes = log2Ceil(beatBytes)
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// AHB has no cache coherence
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in.b.valid := Bool(false)
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in.c.ready := Bool(true)
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in.e.ready := Bool(true)
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// Initial FSM state
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val resetState = Wire(new AHBControlBundle(edgeIn))
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resetState.full := Bool(false)
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resetState.send := Bool(false)
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resetState.first := Bool(true)
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// The stages of the combinational pipeline
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val reg = RegInit(resetState)
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val send = Wire(init = reg)
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val step = Wire(init = send)
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val next = Wire(init = step)
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reg := next
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// Advance the FSM based on the result of this AHB beat
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when (send.send && !out.hreadyout) /* retry AHB */ {
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step.full := Bool(true)
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step.send := Bool(true)
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} .elsewhen (send.full && !send.send) /* retry beat */ {
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step.full := Bool(true)
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step.send := Bool(false)
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} .elsewhen (send.full && !send.last) /* continue burst */ {
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step.full := Bool(true)
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step.send := Bool(false) // => looks like a retry to injector
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step.first := Bool(false)
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step.last := (if (lgBytes + 1 >= lgMax) Bool(true) else
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!((UIntToOH1(send.size, lgMax) & ~send.addr) >> (lgBytes + 1)).orR())
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step.addr := Cat(send.addr(edgeIn.bundle.addressBits-1, lgMax), send.addr(lgMax-1, 0) + UInt(beatBytes))
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} .otherwise /* new burst */ {
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step.full := Bool(false)
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step.send := Bool(false)
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step.first := Bool(true)
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}
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val d_block = Wire(Bool())
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val pre = if (a_pipe) step else reg
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val post = if (a_pipe) next else send
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// Transform TL size into AHB hsize+hburst
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val a_sizeDelta = Cat(UInt(0, width = 1), in.a.bits.size) - UInt(lgBytes+1)
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val a_singleBeat = Bool(lgBytes >= lgMax) || a_sizeDelta(edgeIn.bundle.sizeBits)
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val a_logBeats1 = a_sizeDelta(edgeIn.bundle.sizeBits-1, 0)
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// Pulse this every time we commit to sending an AHB request
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val a_commit = Wire(Bool())
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// Inject A channel into FSM
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when (pre.send) /* busy */ {
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a_commit := Bool(false)
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in.a.ready := Bool(false)
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} .elsewhen (pre.full) /* retry beat (or continue burst) */ {
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post.send := !d_block && (!pre.write || in.a.valid)
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post.data := in.a.bits.data
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a_commit := !d_block && !pre.write // only read beats commit to a D beat answer
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in.a.ready := !d_block && pre.write
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} .otherwise /* new burst */ {
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a_commit := in.a.fire() // every first beat commits to a D beat answer
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in.a.ready := !d_block
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when (in.a.fire()) {
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post.full := Bool(true)
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post.send := Bool(true)
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post.last := a_singleBeat
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post.write := edgeIn.hasData(in.a.bits)
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post.size := in.a.bits.size
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post.source:= in.a.bits.source
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post.hsize := Mux(a_singleBeat, in.a.bits.size, UInt(lgBytes))
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post.hburst:= Mux(a_singleBeat, BURST_SINGLE, (a_logBeats1<<1) | UInt(1))
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post.addr := in.a.bits.address
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post.data := in.a.bits.data
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}
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}
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out.hmastlock := Bool(false) // for now
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out.htrans := Mux(send.send, Mux(send.first, TRANS_NONSEQ, TRANS_SEQ), Mux(send.first, TRANS_IDLE, TRANS_BUSY))
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out.hsel := send.send || !send.first
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out.hready := out.hreadyout
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out.hwrite := send.write
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out.haddr := send.addr
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out.hsize := send.hsize
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out.hburst := send.hburst
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out.hprot := PROT_DEFAULT
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out.hwdata := RegEnable(send.data, out.hreadyout)
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// We need a skidpad to capture D output:
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// We cannot know if the D response will be accepted until we have
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// presented it on D as valid. We also can't back-pressure AHB in the
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// data phase. Therefore, we must have enough space to save the data
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// phase result. Whenever we have a queued response, we can not allow
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// AHB to present new responses, so we must quash the address phase.
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// data phase. Therefore, we must have enough space to save the all
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// commited AHB requests (A+D phases = 2). To decouple d_ready from
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// a_ready and htrans, we add another entry for a_pipe=true.
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val depth = if (a_pipe) 3 else 2
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val d = Wire(in.d)
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in.d <> Queue(d, 1, flow = true)
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val a_quash = in.d.valid && !in.d.ready
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in.d <> Queue(d, depth, flow=true)
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assert (!d.valid || d.ready)
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val d_flight = RegInit(UInt(0, width = 2))
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assert (d_flight <= UInt(depth))
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d_flight := d_flight + a_commit.asUInt - in.d.fire().asUInt
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d_block := d_flight >= UInt(depth)
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// Record what is coming out in d_phase
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val d_valid = RegInit(Bool(false))
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val d_hasData = Reg(Bool())
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val d_error = Reg(Bool())
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val d_addr_lo = Reg(UInt(width = lgBytes))
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val d_source = Reg(UInt())
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val d_size = Reg(UInt())
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val d_write = RegEnable(send.write, out.hreadyout)
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val d_source = RegEnable(send.source, out.hreadyout)
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val d_addr = RegEnable(send.addr, out.hreadyout)
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val d_size = RegEnable(send.size, out.hreadyout)
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when (out.hreadyout) { d_error := d_error || out.hresp }
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when (d.fire()) { d_valid := Bool(false) }
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d.valid := d_valid && out.hreadyout
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d.bits := edgeIn.AccessAck(d_addr_lo, UInt(0), d_source, d_size, out.hrdata, out.hresp || d_error)
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d.bits.opcode := Mux(d_hasData, TLMessages.AccessAckData, TLMessages.AccessAck)
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// We need an irrevocable input for AHB to stall on read bursts
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// We also need the values to NOT change when valid goes low => 1 entry only
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val a = Queue(in.a, 1, flow = combinational, pipe = !combinational)
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val a_valid = a.valid && !a_quash
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// This is lot like TLEdge.firstlast, but counts beats also for single-beat TL types
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val a_size = edgeIn.size(a.bits)
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val a_beats1 = UIntToOH1(a_size, lgMax) >> lgBytes
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val a_counter = RegInit(UInt(0, width = log2Up(maxTransfer/beatBytes)))
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val a_counter1 = a_counter - UInt(1)
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val a_first = a_counter === UInt(0)
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val a_last = a_counter === UInt(1) || a_beats1 === UInt(0)
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val a_offset = (a_beats1 & ~a_counter1) << lgBytes
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val a_hasData = edgeIn.hasData(a.bits)
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// Expand no-data A-channel requests into multiple beats
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a.ready := (a_hasData || a_last) && out.hreadyout && !a_quash
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when (a_valid && out.hreadyout) {
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a_counter := Mux(a_first, a_beats1, a_counter1)
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d_valid := !a_hasData || a_last
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// Record what will be in the data phase
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when (a_first) {
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d_hasData := !a_hasData
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d_error := Bool(false)
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d_addr_lo := a.bits.address
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d_source := a.bits.source
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d_size := a.bits.size
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}
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when (out.hreadyout) {
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d_valid := send.send && (send.last || !send.write)
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when (out.hresp) { d_error := d_write }
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when (send.first) { d_error := Bool(false) }
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}
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// Transform TL size into AHB hsize+hburst
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val a_size_bits = a_size.getWidth
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val a_sizeDelta = Cat(UInt(0, width = 1), a_size) - UInt(lgBytes+1)
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val a_singleBeat = a_sizeDelta(a_size_bits)
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val a_logBeats1 = a_sizeDelta(a_size_bits-1, 0)
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d.valid := d_valid && out.hreadyout
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d.bits := edgeIn.AccessAck(d_addr, UInt(0), d_source, d_size, out.hrdata, out.hresp || d_error)
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d.bits.opcode := Mux(d_write, TLMessages.AccessAck, TLMessages.AccessAckData)
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out.hmastlock := Bool(false) // for now
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out.htrans := Mux(a_valid, Mux(a_first, TRANS_NONSEQ, TRANS_SEQ), Mux(a_first, TRANS_IDLE, TRANS_BUSY))
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out.hsel := a_valid || !a_first
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out.hready := out.hreadyout
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out.hwrite := a_hasData
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out.haddr := a.bits.address | a_offset
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out.hsize := Mux(a_singleBeat, a.bits.size, UInt(lgBytes))
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out.hburst := Mux(a_singleBeat, BURST_SINGLE, (a_logBeats1<<1) | UInt(1))
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out.hprot := PROT_DEFAULT
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out.hwdata := RegEnable(a.bits.data, a.fire())
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// AHB has no cache coherence
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in.b.valid := Bool(false)
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in.c.ready := Bool(true)
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in.e.ready := Bool(true)
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}
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}
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}
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@ -129,8 +189,8 @@ class TLToAHB(val combinational: Boolean = true)(implicit p: Parameters) extends
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object TLToAHB
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{
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// applied to the TL source node; y.node := TLToAHB()(x.node)
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def apply(combinational: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AHBOutwardNode = {
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val ahb = LazyModule(new TLToAHB(combinational))
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def apply(a_pipe: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AHBOutwardNode = {
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val ahb = LazyModule(new TLToAHB(a_pipe))
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ahb.node := x
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ahb.node
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}
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