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coreplex: make rational+synchronous crossing configurable (#688)

This commit is contained in:
Wesley W. Terpstra 2017-04-19 16:16:05 -07:00 committed by GitHub
parent 408107447c
commit b4d17c76d1
3 changed files with 13 additions and 13 deletions
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8
src/main/scala/coreplex/Configs.scala
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@ -20,7 +20,7 @@ class BaseCoreplexConfig extends Config ((site, here, up) => {
case ASIdBits => 0
case XLen => 64 // Applies to all cores
case BuildCore => (p: Parameters) => new Rocket()(p)
case RocketCrossing => Synchronous
case RocketCrossing => SynchronousCrossing()
case RocketTilesKey => Nil
case DMKey => DefaultDebugModuleConfig(site(XLen))
case NTiles => site(RocketTilesKey).size
@ -211,13 +211,13 @@ class WithBootROMFile(bootROMFile: String) extends Config((site, here, up) => {
})
class WithSynchronousRocketTiles extends Config((site, here, up) => {
case RocketCrossing => Synchronous
case RocketCrossing => SynchronousCrossing()
})
class WithAynchronousRocketTiles(depth: Int, sync: Int) extends Config((site, here, up) => {
case RocketCrossing => Asynchronous(depth, sync)
case RocketCrossing => AsynchronousCrossing(depth, sync)
})
class WithRationalRocketTiles extends Config((site, here, up) => {
case RocketCrossing => Rational
case RocketCrossing => RationalCrossing()
})

16
src/main/scala/coreplex/RocketTiles.scala
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@ -11,9 +11,9 @@ import uncore.tilelink2._
import util._
sealed trait ClockCrossing
case object Synchronous extends ClockCrossing
case object Rational extends ClockCrossing
case class Asynchronous(depth: Int, sync: Int = 2) extends ClockCrossing
case class SynchronousCrossing(params: BufferParams = BufferParams.default) extends ClockCrossing
case class RationalCrossing(direction: RationalDirection = FastToSlow) extends ClockCrossing
case class AsynchronousCrossing(depth: Int, sync: Int = 2) extends ClockCrossing
case object RocketTilesKey extends Field[Seq[RocketTileParams]]
case object RocketCrossing extends Field[ClockCrossing]
@ -47,9 +47,9 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
lip.foreach { intBar.intnode := _ } // lip
crossing match {
case Synchronous => {
case SynchronousCrossing(params) => {
val wrapper = LazyModule(new SyncRocketTile(c, i)(pWithExtra))
val buffer = LazyModule(new TLBuffer)
val buffer = LazyModule(new TLBuffer(params))
val fixer = LazyModule(new TLFIFOFixer)
buffer.node :=* wrapper.masterNode
fixer.node :=* buffer.node
@ -62,7 +62,7 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
wrapper.module.io.resetVector := io.resetVector
}
}
case Asynchronous(depth, sync) => {
case AsynchronousCrossing(depth, sync) => {
val wrapper = LazyModule(new AsyncRocketTile(c, i)(pWithExtra))
val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
val source = LazyModule(new TLAsyncCrossingSource(sync))
@ -80,9 +80,9 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
wrapper.module.io.resetVector := io.resetVector
}
}
case Rational => {
case RationalCrossing(direction) => {
val wrapper = LazyModule(new RationalRocketTile(c, i)(pWithExtra))
val sink = LazyModule(new TLRationalCrossingSink(util.FastToSlow))
val sink = LazyModule(new TLRationalCrossingSink(direction))
val source = LazyModule(new TLRationalCrossingSource)
val fixer = LazyModule(new TLFIFOFixer)
sink.node :=* wrapper.masterNode

2
src/main/scala/util/RationalCrossing.scala
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@ -114,7 +114,7 @@ class RationalCrossingSink[T <: Data](gen: T, direction: RationalDirection = Sym
}
}
class RationalCrossing[T <: Data](gen: T, direction: RationalDirection = Symmetric) extends Module
class RationalCrossingFull[T <: Data](gen: T, direction: RationalDirection = Symmetric) extends Module
{
val io = new CrossingIO(gen)