riscv
/
rocket-chip
1
0
Fork 0
Code Releases Activity

debug: Use proper write-1-to-clear ABSTRACTCS.cmderr behavior (because fesvr code is using correct spec)

This commit is contained in:
Megan Wachs 2017-03-28 21:14:22 -07:00
parent ca9a5a1cf7
commit 375a039279
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/uncore/devices/debug/Debug.scala
View File

@ -617,8 +617,8 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrHaltResume.id.U
}.otherwise {
//TODO: Should be write-1-to-clear & ~ABSTRACTCSWrData.cmderr
when (ABSTRACTCSWrEn && ABSTRACTCSWrData.cmderr === 0.U){
ABSTRACTCSReg.cmderr := 0.U
when (ABSTRACTCSWrEn /* && ABSTRACTCSWrData.cmderr === 0.U*/){
ABSTRACTCSReg.cmderr := ABSTRACTCSReg.cmderr & ~(ABSTRACTCSWrData.cmderr);
}
}
}